From patchwork Tue Jul 9 12:31:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 13727820 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 648D6C2BD09 for ; Tue, 9 Jul 2024 12:33:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=2Ftp52qaVEIyfA+eCOHTXDtb7Y99eq7w3TgUMJvcz90=; b=IL1dQvqVQBKUcXxIBWh02ZyJ4a 4m9587/b892l6QT+EWZ/ePNXoGF6oaFN36SypYN2arcnIcze6SROzEfh8Olfv1j7yvAFiKwtRTPKt 5/lhnxDrNj/MvRJzRWEJOphmG0w5hmW8qqdVObRMfKk81YWKczXHEbcGtlPnPSEeW/TH53wafKlce UOEHeHIIu8AjvQNC488vAZB/gYajR7mRvnj/vEscqbHbupAvPPJVgFG6P4tSxIx8iSGyQ/YXJu/t6 KsLN1EqJgUydgcT5AEwH8ysEam2zWDkIVc14bw633UjhSNfZBuJy1dJvLLcaAtjATg0qQ0fV2yqWq TROaTOQA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sRA1u-000000078yu-2usA; Tue, 09 Jul 2024 12:33:10 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sRA0b-000000078Le-2kua; Tue, 09 Jul 2024 12:31:51 +0000 Received: from i5e860d18.versanet.de ([94.134.13.24] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1sRA0U-00074P-6m; Tue, 09 Jul 2024 14:31:42 +0200 From: Heiko Stuebner To: mturquette@baylibre.com, sboyd@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de, quentin.schulz@cherry.de, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH 3/6] arm64: dts: rockchip: fix the pcie clock generator on Rock 5 ITX Date: Tue, 9 Jul 2024 14:31:18 +0200 Message-Id: <20240709123121.1452394-4-heiko@sntech.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240709123121.1452394-1-heiko@sntech.de> References: <20240709123121.1452394-1-heiko@sntech.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240709_053149_883593_FF28D66F X-CRM114-Status: GOOD ( 16.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Rock 5 ITX uses two PCIe controllers to drive both a M.2 slot and its SATA controller with 2 lanes each. The supply for the clock generator is the same that supplies the M.2 slot, but the SATA controller port is supplied by a different rail. This leads to the effect that if the PCIe30x4 controller for the M.2 probes first, everything works normally. But if the PCIe30x2 controller that is connected to the SATA controller probes first, it will hang on the first DBI read as nothing will have enabled the refclock before. Fix this by describing the clock generator with its supplies so that both controllers can reference it as needed. Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-rock-5itx.dts | 34 +++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5itx.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5itx.dts index 41d92ceeeb09c..21fb3d940b489 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5itx.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5itx.dts @@ -77,6 +77,15 @@ hdd-led2 { }; }; + /* Unnamed clock generator: 100MHz,3.3V,3225 */ + pcie30_port0_refclk: pcie30_port1_refclk: pcie-clock-generator { + compatible = "clock-generator"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie30_refclk"; + vdd-supply = <&vcc3v3_pi6c_05>; + }; + fan0: pwm-fan { compatible = "pwm-fan"; #cooling-cells = <2>; @@ -151,13 +160,14 @@ vcc3v3_lan: vcc3v3_lan_phy2: regulator-vcc3v3-lan { vin-supply = <&vcc_3v3_s3>; }; - vcc3v3_mkey: regulator-vcc3v3-mkey { + /* The PCIE30x4_PWREN_H controls two regulators */ + vcc3v3_mkey: vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 { compatible = "regulator-fixed"; enable-active-high; gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie30x4_pwren_h>; - regulator-name = "vcc3v3_mkey"; + regulator-name = "vcc3v3_pi6c_05"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; startup-delay-us = <5000>; @@ -519,6 +529,14 @@ &pcie30phy { /* ASMedia ASM1164 Sata controller */ &pcie3x2 { + clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, + <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, + <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>, + <&pcie30_port1_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe", + "ref"; pinctrl-names = "default"; pinctrl-0 = <&pcie30x2_perstn_m1_l>; reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; @@ -528,6 +546,18 @@ &pcie3x2 { /* M.2 M.key */ &pcie3x4 { + /* + * The board has a gpio-controlled "pcie_refclk" generator, + * so add it to the list of clocks. + */ + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>, + <&pcie30_port0_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe", + "ref"; num-lanes = <2>; pinctrl-names = "default"; pinctrl-0 = <&pcie30x4_perstn_m1_l>;