From patchwork Mon Jul 15 09:57:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikandan Muralidharan X-Patchwork-Id: 13733240 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8176AC3DA5D for ; Mon, 15 Jul 2024 09:59:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=8T2SGK7gHZOh+/NMpW/QWm5SScliGFloYL80cI/F1Qs=; b=rCtxgd3tYEM9X6c5QBKO53xLD5 NIyDXSJ/RPgfd9Ttc5qhulg1rqGzjUEA2qEU2G9Q5f5muG3hSAAQJj5T99DLQm2anmo4gxkx4O85/ QPGwIYMVdd7jGd5m4NkR4p+Mq/qDCApILLA1B9aIo/YyW0EQ5wrFhrrUPgm5Y0UGqFnZMCyjBD6P3 s+xgKfkTTzzk6k398qzp9GBG8qb1A7hXWlDScnaNu8dWzQvgFY36ePWTIJJQEDMde2cjuk/DxMXxY KgpMIKPqXCZef5bcaC1gISogj1k1xKA6JtGbuMsMss7NnZlU2Bhl5hKicaAijh9aMhsHDGut4tzdX ceREy1Aw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTITr-00000006cfV-3P1N; Mon, 15 Jul 2024 09:58:51 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTITU-00000006cTn-09N3 for linux-arm-kernel@lists.infradead.org; Mon, 15 Jul 2024 09:58:30 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1721037508; x=1752573508; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rYf9sUvhDqpSsdpQkGFIz8xXu7hFGMrK2RcSKdTIOzk=; b=g+G1W/Dv3VgBcdu7OKB3dNgkucRBXYRJPHEXU2xkR4+r2qF4Z5VZ68i6 4liQSYelRWK2x/shqADarFFXmAn9dlD51fQ+WDwh2BqUFRddla65phUvN UXg8ujNQNuWQynzXAXvIqb4TnGzyIoVWwpysELV+ev9eDK9Ibi491v/Ir 2x39YPK5+quVv3/6UPWLeJ1C+LgpOLlXL0rtMqOGtG+KAQE8RKs0+y+KM fSX0qXBe39TFRx6Y+E1rhcSF7eTcwEpP4ikSIyVvei+1NKKfym4kk/832 Z2ZBlslfDoK0BJ0ARzOVcBbvyxnVYWKJC0AeUWYQTaUr3Pb6GUlT8u6Mt g==; X-CSE-ConnectionGUID: J1GDDvyAS1e0dCw8Izmz8Q== X-CSE-MsgGUID: Z2OnNiNeTXGzRBanyekvWQ== X-IronPort-AV: E=Sophos;i="6.09,210,1716274800"; d="scan'208";a="29237608" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 15 Jul 2024 02:58:27 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 15 Jul 2024 02:58:02 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 15 Jul 2024 02:57:52 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 1/4] dt-bindings: display: bridge: add sam9x75-mipi-dsi binding Date: Mon, 15 Jul 2024 15:27:33 +0530 Message-ID: <20240715095736.618246-2-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240715095736.618246-1-manikandan.m@microchip.com> References: <20240715095736.618246-1-manikandan.m@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240715_025828_211806_F62505B2 X-CRM114-Status: GOOD ( 15.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: manikandan.m@microchip.com, Hari.PrasathGE@microchip.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the 'sam9x75-mipi-dsi' compatible binding, which describes the Microchip's specific wrapper for the Synopsys DesignWare MIPI DSI HOST Controller for the sam9x75 series System-on-Chip (SoC) devices. Signed-off-by: Manikandan Muralidharan --- changes in v2: - List the clocks with description - remove describing 'remove-endpoint' properties - remove unused label, node and fix example DT indentation - cosmetic fixes --- .../bridge/microchip,sam9x75-mipi-dsi.yaml | 116 ++++++++++++++++++ 1 file changed, 116 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-mipi-dsi.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-mipi-dsi.yaml new file mode 100644 index 000000000000..ef8541d05219 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-mipi-dsi.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/microchip,sam9x75-mipi-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip SAM9X75 MIPI DSI Controller + +maintainers: + - Manikandan Muralidharan + +description: + Microchip specific extensions or wrapper to the Synopsys Designware MIPI DSI. + The MIPI Display Serial Interface (DSI) Host Controller implements all + protocol functions defined in the MIPI DSI Specification.The DSI Host + provides an interface between the LCD Controller (LCDC) and the MIPI D-PHY, + allowing communication with a DSI-compliant display. + +allOf: + - $ref: /schemas/display/dsi-controller.yaml# + +properties: + compatible: + const: microchip,sam9x75-mipi-dsi + + reg: + maxItems: 1 + + clocks: + items: + - description: + Peripheral clock for the hardware block functionality + - description: + Generic clock to drive the D-PHY PLL block + + clock-names: + items: + - const: pclk + - const: refclk + + microchip,sfr: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to Special Function Register (SFR) node.To enable the DSI/CSI + selection bit in SFR's ISS Configuration Register. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + DSI Input port node, connected to the LCDC RGB output port. + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + DSI Output port node, connected to a panel or a bridge input port. + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - ports + +unevaluatedProperties: false + +examples: + - | + #include + #include + + dsi@f8054000 { + compatible = "microchip,sam9x75-mipi-dsi"; + reg = <0xf8054000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 55>; + clock-names = "pclk", "refclk"; + microchip,sfr = <&sfr>; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&hlcdc_panel_output>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; + }; + }; + }; +...