| Message ID | 20240715105156.18388-12-kabel@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | armada-370-xp irqchip updates round 5 | expand |
On Mon, Jul 15 2024 at 12:51, Marek Behún wrote: > Use MPIC_PER_CPU_IRQS_NR (29) bound instead of BITS_PER_LONG (32) when > iterating the bits of the per-CPU interrupt cause register, since there > are only 29 per-CPU interrupts. The top 3 bits are always zero anyway, > so this may save a couple of cycles in the interrupt handler. I seriously doubt that it saves a single cycle, but adjusting the limit is correct by itself. Thanks, tglx
diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index 78d9c7699972..1db9160da20a 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -683,7 +683,7 @@ static void mpic_handle_cascade_irq(struct irq_desc *desc) cause = readl_relaxed(mpic->per_cpu + MPIC_PPI_CAUSE); cpuid = cpu_logical_map(smp_processor_id()); - for_each_set_bit(i, &cause, BITS_PER_LONG) { + for_each_set_bit(i, &cause, MPIC_PER_CPU_IRQS_NR) { irqsrc = readl_relaxed(mpic->base + MPIC_INT_SOURCE_CTL(i)); /* Check if the interrupt is not masked on current CPU.
Use MPIC_PER_CPU_IRQS_NR (29) bound instead of BITS_PER_LONG (32) when iterating the bits of the per-CPU interrupt cause register, since there are only 29 per-CPU interrupts. The top 3 bits are always zero anyway, so this may save a couple of cycles in the interrupt handler. Signed-off-by: Marek Behún <kabel@kernel.org> --- drivers/irqchip/irq-armada-370-xp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)