From patchwork Mon Jul 15 10:51:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 13733321 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6BB54C3DA5D for ; Mon, 15 Jul 2024 10:55:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc: To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=w+ZPzl78i3kwckrb/ZQy7s0+zhNMdwWctIqOBI9Ec4c=; b=wUIP0w/BHD6anW/sGO0PjJhXRl 8K5CxE7+k2MSr1LpT35onRN57yCrAY+W6jDelvFdG85yVLRutYeNGSmP4QjEQ7UNpjWbatyXnFIeh zj2/eejw8IQQbcqZjnVFHD/m65ny3PJjymsO9jq9nPFXWsGVVAgc/i6JjyInfKhYHdOb2vLjwn/or rRCJ7Zv7gfL+GS1t14c8qoLbpGF7RbBuTDtromYExYbo8HA/tXorMbJR7tdt+ylhgIi4emAf5kkV4 rYMffNvY+cn+GCSuzOKWIf0YKGj6ZA+4sB+AI0owbeR2mg7JWi94iCZ1fUZWaH04wtfpRXZFgLIf1 o/D0g7Dw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTJMv-00000006mRR-2JnY; Mon, 15 Jul 2024 10:55:45 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sTJJt-00000006lVS-38Qj for linux-arm-kernel@lists.infradead.org; Mon, 15 Jul 2024 10:52:39 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 12234CE0EEF; Mon, 15 Jul 2024 10:52:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2FE5AC32782; Mon, 15 Jul 2024 10:52:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721040755; bh=bsfrZo4AmleFmLAwB23grY53SRdnkkh2TBIbMYP6ICk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oTvMALi2SzRqg21AeHBIJvdeV6SosJp5l4MJ1TTNuToduW8sHKSrv79mdBtp7wVxj FN5rKb+KTmp8UcTTHrK1D41C3kthNva+2pgOKf0cwMVqk5IDF9svimHPD/jqWicaqd hoCxB/egyWlIkpLAD+kVMuz8P3xXugou1orPyevW6wGqnMH57JFKx/amrEWsZlLfP8 FTcMawZ/1RMdpwSiZumHaev++lvDcg+JfulrX60FC4if0yeQEEYjVqIGx7CSX5pjpg 4MRl+5C8AKeCgcwz8j4ehlggXp1L+xKOnqAizEWMnb2XU2dYtYTupxyNE4PKpVDaId pD262/46j2QMw== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, arm@kernel.org, Andy Shevchenko , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 12/13] irqchip/armada-370-xp: Allow mapping only per-CPU interrupts Date: Mon, 15 Jul 2024 12:51:55 +0200 Message-ID: <20240715105156.18388-13-kabel@kernel.org> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240715105156.18388-1-kabel@kernel.org> References: <20240715105156.18388-1-kabel@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240715_035238_005288_0B955F32 X-CRM114-Status: GOOD ( 14.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On platforms where MPIC is not the top-level interrupt controller the driver currently only supports handling of the per-CPU interrupts (the first 29 interrupts). This is obvious from the code of mpic_handle_cascade_irq(), where we read only one cause register. Bound the number of available interrupts in the IRQ domain to 29 for these platforms. The corresponding device-trees refer only to per-CPU interrupts via MPIC, the other interrupts are referred to via GIC. Signed-off-by: Marek Behún --- drivers/irqchip/irq-armada-370-xp.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index 1db9160da20a..3cae6ceacc73 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -858,6 +858,19 @@ static int __init mpic_of_init(struct device_node *node, for (irq_hw_number_t i = 0; i < nr_irqs; i++) writel(i, mpic->base + MPIC_INT_CLEAR_ENABLE); + /* + * Initialize mpic->parent_irq before calling any other functions, since + * it is used to distinguish between IPI and non-IPI platforms. + */ + mpic->parent_irq = irq_of_parse_and_map(node, 0); + + /* + * On non-IPI platforms the driver currently supports only the per-CPU + * interrupts (the first 29 interrupts). See mpic_handle_cascade_irq(). + */ + if (!mpic_is_ipi_available(mpic)) + nr_irqs = MPIC_PER_CPU_IRQS_NR; + mpic->domain = irq_domain_add_linear(node, nr_irqs, &mpic_irq_ops, mpic); if (!mpic->domain) { pr_err("%pOF: Unable to add IRQ domain\n", node); @@ -866,12 +879,6 @@ static int __init mpic_of_init(struct device_node *node, irq_domain_update_bus_token(mpic->domain, DOMAIN_BUS_WIRED); - /* - * Initialize mpic->parent_irq before calling any other functions, since - * it is used to distinguish between IPI and non-IPI platforms. - */ - mpic->parent_irq = irq_of_parse_and_map(node, 0); - /* Setup for the boot CPU */ mpic_perf_init(mpic); mpic_smp_cpu_init(mpic);