diff mbox series

[v2,3/6] aarch64: Remove TSCXT bit set from SCTLR_EL2_RESET

Message ID 20240716142906.1502802-4-luca.fancellu@arm.com (mailing list archive)
State New, archived
Headers show
Series Add Armv8-R AArch64 support | expand

Commit Message

Luca Fancellu July 16, 2024, 2:29 p.m. UTC 
From the specification SCTLR_EL2.TSCXT is RES1 only "When
FEAT_CSV2_2 is not implemented, FEAT_CSV2_1p2 is not
implemented, HCR_EL2.E2H == 1 and HCR_EL2.TGE == 1", so
given that HCR_EL2.E2H is set by bootwrapper before to a
value of zero, the condition above can't happen and from
the specification the bit is RES0.

Fix the macro removing the bit.

Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
---
v2 changes:
 - Add Andre R-by
---
 arch/aarch64/include/asm/cpu.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Mark Rutland July 19, 2024, 10:05 a.m. UTC | #1 
On Tue, Jul 16, 2024 at 03:29:03PM +0100, Luca Fancellu wrote:
> From the specification SCTLR_EL2.TSCXT is RES1 only "When
> FEAT_CSV2_2 is not implemented, FEAT_CSV2_1p2 is not
> implemented, HCR_EL2.E2H == 1 and HCR_EL2.TGE == 1", so
> given that HCR_EL2.E2H is set by bootwrapper before to a
> value of zero, the condition above can't happen and from
> the specification the bit is RES0.
> 
> Fix the macro removing the bit.
> 
> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
> Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Since this is a fix independenny of the rest of the series, I've applied
this on its own and pushed it out.

I'll chew through the rest of the series shortly.

Mark.

> ---
> v2 changes:
>  - Add Andre R-by
> ---
>  arch/aarch64/include/asm/cpu.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
> index 124ef916ddfc..846b89f8405d 100644
> --- a/arch/aarch64/include/asm/cpu.h
> +++ b/arch/aarch64/include/asm/cpu.h
> @@ -30,8 +30,8 @@
>  	 BIT(11) | BIT(5) | BIT(4))
>  
>  #define SCTLR_EL2_RES1							\
> -	(BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(20) | BIT(18) |	\
> -	 BIT(16) | BIT(11) | BIT(5) | BIT(4))
> +	(BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(18) | BIT(16) |	\
> +	 BIT(11) | BIT(5) | BIT(4))
>  
>  #define SCTLR_EL1_RES1							\
>  	(BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(20) | BIT(11) |	\
> -- 
> 2.34.1
>
diff mbox series

Patch

diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index 124ef916ddfc..846b89f8405d 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -30,8 +30,8 @@ 
 	 BIT(11) | BIT(5) | BIT(4))
 
 #define SCTLR_EL2_RES1							\
-	(BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(20) | BIT(18) |	\
-	 BIT(16) | BIT(11) | BIT(5) | BIT(4))
+	(BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(18) | BIT(16) |	\
+	 BIT(11) | BIT(5) | BIT(4))
 
 #define SCTLR_EL1_RES1							\
 	(BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(20) | BIT(11) |	\