| Message ID | 20240720110455.3043327-1-s-vadapalli@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: ti: k3-j784s4-evm: Use 4 lanes for PCIe0 on EVM | expand |
On 16:34-20240720, Siddharth Vadapalli wrote: > The PCIe0 instance of the PCIe controller on J784S4 SoC supports up to 4 > lanes. Additionally, all 4 lanes of PCIe0 can be utilized on J784S4-EVM > via SERDES1. Since SERDES1 is not being used by any peripheral apart > from PCIe0, use all 4 lanes of SERDES1 for PCIe0. > > Fixes: 27ce26fe52d4 ("arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode") > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> > --- > > Hello, > > This patch is based on linux-next tagged next-20240715. > Patch has been tested on J784S4-EVM. Logs: > https://gist.github.com/Siddharth-Vadapalli-at-TI/2b9b1196ff6b9eac895a7986e5ff4456 > NOTE: Patch applies cleanly on Mainline Linux's latest commit > 3c3ff7be9729 Merge tag 'powerpc-6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux > > Regards, > Siddharth. > > arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts > index ffa38f41679d..ea27519d7b89 100644 > --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts > @@ -1407,10 +1407,11 @@ &serdes1 { > > serdes1_pcie0_link: phy@0 { > reg = <0>; > - cdns,num-lanes = <2>; > + cdns,num-lanes = <4>; > #phy-cells = <0>; > cdns,phy-type = <PHY_TYPE_PCIE>; > - resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; > + resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>, > + <&serdes_wiz1 3>, <&serdes_wiz1 4>; > }; OK - I see the reason why https://lore.kernel.org/all/20240807132054.jcz5fdokc5yk3mbo@entrust/ was missed. Please sync with Manorit to make sure we sequence these correctly - looks to me that this fixup needs to get in first? have you also checked up on AM69-SK ? > }; > > -- > 2.40.1 >
On Wed, Aug 07, 2024 at 08:28:47AM -0500, Nishanth Menon wrote: > On 16:34-20240720, Siddharth Vadapalli wrote: > > The PCIe0 instance of the PCIe controller on J784S4 SoC supports up to 4 > > lanes. Additionally, all 4 lanes of PCIe0 can be utilized on J784S4-EVM > > via SERDES1. Since SERDES1 is not being used by any peripheral apart > > from PCIe0, use all 4 lanes of SERDES1 for PCIe0. > > > > Fixes: 27ce26fe52d4 ("arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode") > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> [...] > > serdes1_pcie0_link: phy@0 { > > reg = <0>; > > - cdns,num-lanes = <2>; > > + cdns,num-lanes = <4>; > > #phy-cells = <0>; > > cdns,phy-type = <PHY_TYPE_PCIE>; > > - resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; > > + resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>, > > + <&serdes_wiz1 3>, <&serdes_wiz1 4>; > > }; > > OK - I see the reason why > https://lore.kernel.org/all/20240807132054.jcz5fdokc5yk3mbo@entrust/ > was missed. > > Please sync with Manorit to make sure we sequence these correctly - > looks to me that this fixup needs to get in first? have you also checked > up on AM69-SK ? J784S4 SoC has 4 instances of PCIe -> PCIe0, PCIe1, PCIe2 and PCIe3. All 4 instances have been described in k3-j784s4-main.dtsi. Of the 4 instances PCIe0 and PCIe1 are brought out on J784S4-EVM. Therefore, k3-j784s4-evm.dts enables only PCIe0 and PCIe1. This patch allocates all 4 lanes of SERDES1 to PCIe0 on J784S4-EVM since no other peripheral is sharing SERDES1 with PCIe0. On AM69-SK, all 4 lanes of SERDES1 have correctly been assigned to PCIe0, due to which no fix is required. J742S2 SoC has 2 instances of PCIe -> PCIe0 and PCIe1. They have the same connections w.r.t. SERDES as J784S4 SoC i.e. PCIe0 -> 4 Lanes of SERDES1 PCIe1 -> 2 Lanes of SERDES0 So PCIe2 and PCIe3 have to be removed from k3-j784s4-j742s2-main-common.dtsi in the patch by Manorit at: https://lore.kernel.org/r/20240731-b4-upstream-j742s2-v3-4-da7fe3aa9e90@ti.com/ and added in k3-j784s4-main.dtsi similar to the "c71_3: dsp@67800000" node. The changes made by this patch (assigning all 4 lanes of SERDES1 to PCIe0) will be applicable to J742S2-EVM as well. Regards, Siddharth.
Hi Siddharth Vadapalli, On Sat, 20 Jul 2024 16:34:55 +0530, Siddharth Vadapalli wrote: > The PCIe0 instance of the PCIe controller on J784S4 SoC supports up to 4 > lanes. Additionally, all 4 lanes of PCIe0 can be utilized on J784S4-EVM > via SERDES1. Since SERDES1 is not being used by any peripheral apart > from PCIe0, use all 4 lanes of SERDES1 for PCIe0. > > I have applied the following to branch ti-k3-dts-next on [1]. Thank you! [1/1] arm64: dts: ti: k3-j784s4-evm: Use 4 lanes for PCIe0 on EVM commit: ba7b9e8408ab866aa0b3c88e406b8934782402d7 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent up the chain during the next merge window (or sooner if it is a relevant bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. [1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index ffa38f41679d..ea27519d7b89 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -1407,10 +1407,11 @@ &serdes1 { serdes1_pcie0_link: phy@0 { reg = <0>; - cdns,num-lanes = <2>; + cdns,num-lanes = <4>; #phy-cells = <0>; cdns,phy-type = <PHY_TYPE_PCIE>; - resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; + resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>, + <&serdes_wiz1 3>, <&serdes_wiz1 4>; }; };
The PCIe0 instance of the PCIe controller on J784S4 SoC supports up to 4 lanes. Additionally, all 4 lanes of PCIe0 can be utilized on J784S4-EVM via SERDES1. Since SERDES1 is not being used by any peripheral apart from PCIe0, use all 4 lanes of SERDES1 for PCIe0. Fixes: 27ce26fe52d4 ("arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode") Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> --- Hello, This patch is based on linux-next tagged next-20240715. Patch has been tested on J784S4-EVM. Logs: https://gist.github.com/Siddharth-Vadapalli-at-TI/2b9b1196ff6b9eac895a7986e5ff4456 NOTE: Patch applies cleanly on Mainline Linux's latest commit 3c3ff7be9729 Merge tag 'powerpc-6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Regards, Siddharth. arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)