From patchwork Tue Jul 23 11:06:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 13739916 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0A3F0C3DA49 for ; Tue, 23 Jul 2024 11:07:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=GFUv5eV1fSxwNGi+jelOJiUsc1L8nwaZRy2O03bkVV8=; b=hGhTkEKl5mQ8dj6T47SNj7/7u1 1SFkiON20jomv0DFh5RHAHEKKNVj7TdcQJgU7BbG/DN39maS9OuM/1sSwV6yikwUVmwostddCqP+0 qbOS1XEaDbhYJWpLgjKnh6xuG7cFtDBwzEUae84hWGjUOSUUt83qfWE/aOSJLTRrWM33uD9k0Zieo pG+65hdn3YqwYqlHokGo1aD2hpd6ZF/V1EXoH6/hYeFG17VIAn7VBYNhr+A0X/4pCGBf5dgbyG4ii 2FHw4dwDzo1epMC+/qxy/9mgvQkZNJ6YwWaJegRSdWM/K8ic4AdHkXXdv3DALSu39jBws9uQ86suk SbvOoopw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sWDMJ-0000000CECt-06fO; Tue, 23 Jul 2024 11:07:07 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sWDLu-0000000CE9C-3Hpv for linux-arm-kernel@lists.infradead.org; Tue, 23 Jul 2024 11:06:44 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D16EF1476; Tue, 23 Jul 2024 04:07:07 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.54.37]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D5C613F73F; Tue, 23 Jul 2024 04:06:40 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: mark.rutland@arm.com, Anshuman Khandual Subject: [boot-wrapper 1/3] aarch64: Enable access into 128 bit system registers from EL2 and below Date: Tue, 23 Jul 2024 16:36:28 +0530 Message-Id: <20240723110630.483871-2-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240723110630.483871-1-anshuman.khandual@arm.com> References: <20240723110630.483871-1-anshuman.khandual@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240723_040642_882291_1665ACBF X-CRM114-Status: UNSURE ( 8.61 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org FEAT_D128 adds 128 bit system registers like PAR_EL1, TTBR0_EL1, TTBR1_EL1, TTBR0_EL2, TTBR1_EL2, TTBR0_EL12, TTBR1_EL12 , VTTBR_EL2, RCWMASK_EL1, and RCWSMASK_EL1. But access into these register from EL2 and below trap to EL3 unless SCR_EL3.D128En is set. Enable access to 128 bit registers when they are implemented. Signed-off-by: Anshuman Khandual --- arch/aarch64/include/asm/cpu.h | 2 ++ arch/aarch64/init.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 124ef91..0b8b463 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -57,6 +57,7 @@ #define SCR_EL3_EnTP2 BIT(41) #define SCR_EL3_TCR2EN BIT(43) #define SCR_EL3_PIEN BIT(45) +#define SCR_EL3_D128En BIT(47) #define HCR_EL2_RES1 BIT(1) @@ -85,6 +86,7 @@ #define ID_AA64MMFR3_EL1_S2PIE BITS(15, 12) #define ID_AA64MMFR3_EL1_S1POE BITS(19, 16) #define ID_AA64MMFR3_EL1_S2POE BITS(23, 20) +#define ID_AA64MMFR3_EL1_D128 BITS(35, 32) #define ID_AA64PFR1_EL1_MTE BITS(11, 8) #define ID_AA64PFR1_EL1_SME BITS(27, 24) diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index 37cb45f..7d9d0d9 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -89,6 +89,9 @@ void cpu_init_el3(void) if (!kernel_is_32bit()) scr |= SCR_EL3_RW; + if (mrs_field(ID_AA64MMFR3_EL1, D128)) + scr |= SCR_EL3_D128En; + msr(SCR_EL3, scr); msr(CPTR_EL3, cptr);