| Message ID | 20240726062639.2609974-3-abin.joseph@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for ADMA | expand |
On 26/07/2024 08:26, Abin Joseph wrote: > ZynqMp DMA IP and AMD Versal Gen 2 DMA IP are similar but have different > interrupt register offset. Create a dedicated compatible string to > support Versal Gen 2 DMA IP with Irq register offset for interrupt > Enable/Disable/Status/Mask functionality. > > > /** > @@ -919,6 +924,9 @@ static int zynqmp_dma_chan_probe(struct zynqmp_dma_device *zdev, > return -EINVAL; > } > > + if (of_device_is_compatible(node, "amd,versal2-dma-1.0")) > + chan->irq_offset = IRQ_REG_OFFSET; Do not sprinkle compatibles, but use match data. Best regards, Krzysztof
On 26-07-24, 11:56, Abin Joseph wrote: > ZynqMp DMA IP and AMD Versal Gen 2 DMA IP are similar but have different > interrupt register offset. Create a dedicated compatible string to > support Versal Gen 2 DMA IP with Irq register offset for interrupt > Enable/Disable/Status/Mask functionality. > > Signed-off-by: Abin Joseph <abin.joseph@amd.com> > --- > drivers/dma/xilinx/zynqmp_dma.c | 17 +++++++++++++---- > 1 file changed, 13 insertions(+), 4 deletions(-) > > diff --git a/drivers/dma/xilinx/zynqmp_dma.c b/drivers/dma/xilinx/zynqmp_dma.c > index f31631bef961..a5d84d746929 100644 > --- a/drivers/dma/xilinx/zynqmp_dma.c > +++ b/drivers/dma/xilinx/zynqmp_dma.c > @@ -22,10 +22,10 @@ > #include "../dmaengine.h" > > /* Register Offsets */ > -#define ZYNQMP_DMA_ISR 0x100 > -#define ZYNQMP_DMA_IMR 0x104 > -#define ZYNQMP_DMA_IER 0x108 > -#define ZYNQMP_DMA_IDS 0x10C > +#define ZYNQMP_DMA_ISR (chan->irq_offset + 0x100) > +#define ZYNQMP_DMA_IMR (chan->irq_offset + 0x104) > +#define ZYNQMP_DMA_IER (chan->irq_offset + 0x108) > +#define ZYNQMP_DMA_IDS (chan->irq_offset + 0x10C) Lower case please > #define ZYNQMP_DMA_CTRL0 0x110 > #define ZYNQMP_DMA_CTRL1 0x114 > #define ZYNQMP_DMA_DATA_ATTR 0x120 > @@ -145,6 +145,9 @@ > #define tx_to_desc(tx) container_of(tx, struct zynqmp_dma_desc_sw, \ > async_tx) > > +/* IRQ Register offset for VersalGen2 */ > +#define IRQ_REG_OFFSET 0x308 > + > /** > * struct zynqmp_dma_desc_ll - Hw linked list descriptor > * @addr: Buffer address > @@ -211,6 +214,7 @@ struct zynqmp_dma_desc_sw { > * @bus_width: Bus width > * @src_burst_len: Source burst length > * @dst_burst_len: Dest burst length > + * @irq_offset: Irq register offset > */ > struct zynqmp_dma_chan { > struct zynqmp_dma_device *zdev; > @@ -235,6 +239,7 @@ struct zynqmp_dma_chan { > u32 bus_width; > u32 src_burst_len; > u32 dst_burst_len; > + u32 irq_offset; > }; > > /** > @@ -919,6 +924,9 @@ static int zynqmp_dma_chan_probe(struct zynqmp_dma_device *zdev, > return -EINVAL; > } > > + if (of_device_is_compatible(node, "amd,versal2-dma-1.0")) > + chan->irq_offset = IRQ_REG_OFFSET; This should be added as driver_data > + > chan->is_dmacoherent = of_property_read_bool(node, "dma-coherent"); > zdev->chan = chan; > tasklet_setup(&chan->tasklet, zynqmp_dma_do_tasklet); > @@ -1162,6 +1170,7 @@ static void zynqmp_dma_remove(struct platform_device *pdev) > > static const struct of_device_id zynqmp_dma_of_match[] = { > { .compatible = "xlnx,zynqmp-dma-1.0", }, > + { .compatible = "amd,versal2-dma-1.0", }, > {} > }; > MODULE_DEVICE_TABLE(of, zynqmp_dma_of_match); > -- > 2.25.1
diff --git a/drivers/dma/xilinx/zynqmp_dma.c b/drivers/dma/xilinx/zynqmp_dma.c index f31631bef961..a5d84d746929 100644 --- a/drivers/dma/xilinx/zynqmp_dma.c +++ b/drivers/dma/xilinx/zynqmp_dma.c @@ -22,10 +22,10 @@ #include "../dmaengine.h" /* Register Offsets */ -#define ZYNQMP_DMA_ISR 0x100 -#define ZYNQMP_DMA_IMR 0x104 -#define ZYNQMP_DMA_IER 0x108 -#define ZYNQMP_DMA_IDS 0x10C +#define ZYNQMP_DMA_ISR (chan->irq_offset + 0x100) +#define ZYNQMP_DMA_IMR (chan->irq_offset + 0x104) +#define ZYNQMP_DMA_IER (chan->irq_offset + 0x108) +#define ZYNQMP_DMA_IDS (chan->irq_offset + 0x10C) #define ZYNQMP_DMA_CTRL0 0x110 #define ZYNQMP_DMA_CTRL1 0x114 #define ZYNQMP_DMA_DATA_ATTR 0x120 @@ -145,6 +145,9 @@ #define tx_to_desc(tx) container_of(tx, struct zynqmp_dma_desc_sw, \ async_tx) +/* IRQ Register offset for VersalGen2 */ +#define IRQ_REG_OFFSET 0x308 + /** * struct zynqmp_dma_desc_ll - Hw linked list descriptor * @addr: Buffer address @@ -211,6 +214,7 @@ struct zynqmp_dma_desc_sw { * @bus_width: Bus width * @src_burst_len: Source burst length * @dst_burst_len: Dest burst length + * @irq_offset: Irq register offset */ struct zynqmp_dma_chan { struct zynqmp_dma_device *zdev; @@ -235,6 +239,7 @@ struct zynqmp_dma_chan { u32 bus_width; u32 src_burst_len; u32 dst_burst_len; + u32 irq_offset; }; /** @@ -919,6 +924,9 @@ static int zynqmp_dma_chan_probe(struct zynqmp_dma_device *zdev, return -EINVAL; } + if (of_device_is_compatible(node, "amd,versal2-dma-1.0")) + chan->irq_offset = IRQ_REG_OFFSET; + chan->is_dmacoherent = of_property_read_bool(node, "dma-coherent"); zdev->chan = chan; tasklet_setup(&chan->tasklet, zynqmp_dma_do_tasklet); @@ -1162,6 +1170,7 @@ static void zynqmp_dma_remove(struct platform_device *pdev) static const struct of_device_id zynqmp_dma_of_match[] = { { .compatible = "xlnx,zynqmp-dma-1.0", }, + { .compatible = "amd,versal2-dma-1.0", }, {} }; MODULE_DEVICE_TABLE(of, zynqmp_dma_of_match);
ZynqMp DMA IP and AMD Versal Gen 2 DMA IP are similar but have different interrupt register offset. Create a dedicated compatible string to support Versal Gen 2 DMA IP with Irq register offset for interrupt Enable/Disable/Status/Mask functionality. Signed-off-by: Abin Joseph <abin.joseph@amd.com> --- drivers/dma/xilinx/zynqmp_dma.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-)