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Fri, 26 Jul 2024 01:26:50 -0500 From: Abin Joseph To: , , , , , , , CC: , , , , , Subject: [PATCH 2/2] dmaengine: zynqmp_dma: Add support for AMD Versal Gen 2 DMA IP Date: Fri, 26 Jul 2024 11:56:39 +0530 Message-ID: <20240726062639.2609974-3-abin.joseph@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240726062639.2609974-1-abin.joseph@amd.com> References: <20240726062639.2609974-1-abin.joseph@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECDB:EE_|CY5PR12MB6407:EE_ X-MS-Office365-Filtering-Correlation-Id: 7fb355c8-e860-4db5-9b76-08dcad3bf264 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: Hxp5PXY2gQt8HEdfRUnFRFo9ZFcU50afphu2mHDlfuDZu+GunfcCWb0F6ItNKF7mKZRrWWcVi0cQHb3z1NzBXNiZfZdAb+tqte4S04axiV74UOtprX/DvTrFV6r9AuyzAOfInBc1jXucbv4HpzsTTwEWvPSGT794cmdCn51WyCNGNLaJAROwQHnzhf/NwtD0Wpphn8MohTKXhzY3C/fn43AkLrYfk5WqQQ/uB7+oKZud0OW4QLAaUmzKB4tyE24YenMd26Aa7xp+YkGHo9hZ5IW4r+2fW+W8NyyR/gTJXV+NsoN47qcfqZbQs+FJs5c6yoRFuk4bEbWLmYUK8ZhJsPObp/b7VOOtGPifCEgJx5ziZT6BsNPf12yeIy/6mG58hLjzS2qB4cWpPy4hcbGkhqZQG5DJIjbs/uJ7rEzfYjlxb4/S1jM5ERcuv0ItKwiEDq8M1rO2L0xRNeVKJ4T4tSnI2wkrXyreSMtVXU0HezydNzAA4lubx12ZvkkFhwcB0zXWIvl7XwCLFTtFR9LPhZ7knHGktA4tei/7Smluy8TEEVjFwO2BV7E7fsYTQU2BrrI2bDifAie1Y/okSi7yQnQ+6ZGE4ogoYF1cQsTw81iUISub9o+Y3LtOUH6ouaJZl/TNxkWrN3fk6+bffZ0DRzn1R6s98gZDwoLpn6sVNt2+8XZQMN+HCza2EHPVLM8OiH3/i3h1Wz/ZtsQ3tSo/n8iXL0SEGKtPSlSgea2JhT5+XqaeNjJhT7JjB3MBAFX8kxtw/rftUjYIqdSGm2BK4MZSNiJrk2o5szpoTUaBD32MbkBRr6OmQrUUXgX/tMPzTjOaMKihVrVJqIt4Ytknk9fIZXNyenuVzXmTjrzziyqflt3VV2ZGB49UaiDpgR/p4L9uu8NmO7NqZyBOfErV6lAk5rr8nRJt+LF/c3/EtpLn6+qR0iKA1iJbPa1pMfQSjMwnc4UIwIAL76GlMaDOt2bNiumCk5iDtaU19HEbBzPEw7RJ8wZtbrkbt27vZD2gifc84alZ9aZhDIq5KN/OyGvzhGF9j/A44onrBDqLuI6XLfzsCa10lJFUxKihg8FgzwOX+dT45uSCTbXgqYeTedZji3Kad3bgUy1WdWdws5v7Hi3APsuWcco1oM95o9WsQV/FG+pIdMaZDiHo57MPhHdCT2U7GMuU4RhrT4l0enWsiFlMw/FwaflYqMDXxJFg2jvp57AISkb7irVGBv+mZ45DfDSXn05+nhhJC8dLzd+nMgd9lcbNg06U30Ipw5I0+WwbpWgtkm2GfW/5Ni3y86ynWC/Q9H9JLKDtf+HvcQUYeNuqnepk5Y0pxySjvhCmBO4UKwMl9rUXzQR0hNjELBBwqd1+HcSk+HPMel19k9+T0Gk7bYYhiRfxHZeoeSmwTC8rgBIla77WKxITJRPDBYJ9y5KpJuyBZfIOka9evGgUoUcbD9cu/VSN2WF3MZT7 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jul 2024 06:26:55.8623 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7fb355c8-e860-4db5-9b76-08dcad3bf264 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECDB.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6407 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240725_232701_512547_01C48C46 X-CRM114-Status: GOOD ( 15.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org ZynqMp DMA IP and AMD Versal Gen 2 DMA IP are similar but have different interrupt register offset. Create a dedicated compatible string to support Versal Gen 2 DMA IP with Irq register offset for interrupt Enable/Disable/Status/Mask functionality. Signed-off-by: Abin Joseph --- drivers/dma/xilinx/zynqmp_dma.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/dma/xilinx/zynqmp_dma.c b/drivers/dma/xilinx/zynqmp_dma.c index f31631bef961..a5d84d746929 100644 --- a/drivers/dma/xilinx/zynqmp_dma.c +++ b/drivers/dma/xilinx/zynqmp_dma.c @@ -22,10 +22,10 @@ #include "../dmaengine.h" /* Register Offsets */ -#define ZYNQMP_DMA_ISR 0x100 -#define ZYNQMP_DMA_IMR 0x104 -#define ZYNQMP_DMA_IER 0x108 -#define ZYNQMP_DMA_IDS 0x10C +#define ZYNQMP_DMA_ISR (chan->irq_offset + 0x100) +#define ZYNQMP_DMA_IMR (chan->irq_offset + 0x104) +#define ZYNQMP_DMA_IER (chan->irq_offset + 0x108) +#define ZYNQMP_DMA_IDS (chan->irq_offset + 0x10C) #define ZYNQMP_DMA_CTRL0 0x110 #define ZYNQMP_DMA_CTRL1 0x114 #define ZYNQMP_DMA_DATA_ATTR 0x120 @@ -145,6 +145,9 @@ #define tx_to_desc(tx) container_of(tx, struct zynqmp_dma_desc_sw, \ async_tx) +/* IRQ Register offset for VersalGen2 */ +#define IRQ_REG_OFFSET 0x308 + /** * struct zynqmp_dma_desc_ll - Hw linked list descriptor * @addr: Buffer address @@ -211,6 +214,7 @@ struct zynqmp_dma_desc_sw { * @bus_width: Bus width * @src_burst_len: Source burst length * @dst_burst_len: Dest burst length + * @irq_offset: Irq register offset */ struct zynqmp_dma_chan { struct zynqmp_dma_device *zdev; @@ -235,6 +239,7 @@ struct zynqmp_dma_chan { u32 bus_width; u32 src_burst_len; u32 dst_burst_len; + u32 irq_offset; }; /** @@ -919,6 +924,9 @@ static int zynqmp_dma_chan_probe(struct zynqmp_dma_device *zdev, return -EINVAL; } + if (of_device_is_compatible(node, "amd,versal2-dma-1.0")) + chan->irq_offset = IRQ_REG_OFFSET; + chan->is_dmacoherent = of_property_read_bool(node, "dma-coherent"); zdev->chan = chan; tasklet_setup(&chan->tasklet, zynqmp_dma_do_tasklet); @@ -1162,6 +1170,7 @@ static void zynqmp_dma_remove(struct platform_device *pdev) static const struct of_device_id zynqmp_dma_of_match[] = { { .compatible = "xlnx,zynqmp-dma-1.0", }, + { .compatible = "amd,versal2-dma-1.0", }, {} }; MODULE_DEVICE_TABLE(of, zynqmp_dma_of_match);