From patchwork Fri Jul 26 11:03:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Chen X-Patchwork-Id: 13742627 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66003C3DA7F for ; Fri, 26 Jul 2024 11:08:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:To:From:Reply-To:Cc:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=VTLWoDFU4jAP+OGSo8ekPMX3sbl8RbyywrS5DH0PzUc=; b=ChXUL8lbqzQilUA47AKZDiSWoS nNx81aVM0AU9loYxdVjRfSQJ4ag6HW743aldYVR4l0Yf+PxOPhvRRGd3DX9uDVKeli5yJ5qtOXCfC 58uKC5coq4bI4RJ5wd3hPwfWq7gB6hZSmUff8jrOgP9wb5nXGgJ+kztfvfDuqg/rTly9/cFqaTNrL 7MHj4JS/Ey1YcmJlSz8vFb7HH1djKWMk8UlSP9ZOWRBzp8AvKNZsKKEZeBvPdK1iQsF6QzvbCJ8dZ jNs3cajzAQyBmeIWhWSq5TYgFoFXJTWjOIis4f89gZUbClMO+aOWBsUJ2hwRhMe6aUnIi0YVvTInU dHuKp/PA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sXInm-00000003eiG-0oIr; Fri, 26 Jul 2024 11:07:58 +0000 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sXIkJ-00000003dJh-3tSe for linux-arm-kernel@lists.infradead.org; Fri, 26 Jul 2024 11:04:25 +0000 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 26 Jul 2024 19:04:00 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 26 Jul 2024 19:04:00 +0800 From: Kevin Chen To: , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v1 08/10] arm64: dts: aspeed: Add initial AST27XX device tree Date: Fri, 26 Jul 2024 19:03:53 +0800 Message-ID: <20240726110355.2181563-9-kevin_chen@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240726110355.2181563-1-kevin_chen@aspeedtech.com> References: <20240726110355.2181563-1-kevin_chen@aspeedtech.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240726_040423_996461_11098AD3 X-CRM114-Status: GOOD ( 11.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi | 217 ++++++++++++++++++++++ 2 files changed, 218 insertions(+) create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 21cd3a87f385..c909c19dc5dd 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -34,3 +34,4 @@ subdir-y += tesla subdir-y += ti subdir-y += toshiba subdir-y += xilinx +subdir-y += aspeed diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi new file mode 100644 index 000000000000..858ab95251e4 --- /dev/null +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +#include +#include +#include +#include + +/ { + model = "Aspeed BMC"; + compatible = "aspeed,ast2700"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + aliases { + serial12 = &uart12; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a35"; + enable-method = "psci"; + device_type = "cpu"; + reg = <0>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&l2>; + }; + + cpu@1 { + compatible = "arm,cortex-a35"; + enable-method = "psci"; + device_type = "cpu"; + reg = <1>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&l2>; + }; + + cpu@2 { + compatible = "arm,cortex-a35"; + enable-method = "psci"; + device_type = "cpu"; + reg = <2>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&l2>; + }; + + cpu@3 { + compatible = "arm,cortex-a35"; + enable-method = "psci"; + device_type = "cpu"; + reg = <3>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + }; + }; + + pmu { + compatible = "arm,cortex-a35-pmu"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + gic: interrupt-controller@12200000 { + compatible = "arm,gic-v3"; + interrupts = ; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&gic>; + #redistributor-regions = <1>; + reg = <0 0x12200000 0 0x10000>, //GICD + <0 0x12280000 0 0x80000>, //GICR + <0 0x40440000 0 0x1000>; //GICC + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + arm,cpu-registers-not-fw-configured; + always-on; + }; + + soc0: soc@10000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + soc0_sram: sram@10000000 { + compatible = "mmio-sram"; + reg = <0x0 0x10000000 0x0 0x20000>; /* 128KiB SRAM on soc0 */ + ranges = <0x0 0x0 0x0 0x10000000 0x0 0x20000>; + #address-cells = <2>; + #size-cells = <2>; + no-memory-wc; + + exported@0 { + reg = <0 0x0 0 0x20000>; + export; + }; + }; + + syscon0: syscon@12c02000 { + compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd"; + reg = <0x0 0x12c02000 0x0 0x1000>; + ranges = <0x0 0x0 0 0x12c02000 0 0x1000>; + #address-cells = <2>; + #size-cells = <2>; + #clock-cells = <1>; + #reset-cells = <1>; + + silicon-id@0 { + compatible = "aspeed,ast2700-silicon-id", "aspeed,silicon-id"; + reg = <0 0x0 0 0x4>; + }; + + scu_ic0: interrupt-controller@1D0 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2700-scu-ic0"; + reg = <0 0x1d0 0 0xc>; + interrupts = ; + interrupt-controller; + }; + + scu_ic1: interrupt-controller@1E0 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2700-scu-ic1"; + reg = <0 0x1e0 0 0xc>; + interrupts = ; + interrupt-controller; + }; + + soc0_rst: reset-controller@200 { + reg = <0 0x200 0 0x40>; + }; + + soc0_clk: clock-controller@240 { + reg = <0 0x240 0 0x1c0>; + }; + }; + + }; + + soc1: soc@14000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + syscon1: syscon@14c02000 { + compatible = "aspeed,ast2700-scu1", "syscon", "simple-mfd"; + reg = <0x0 0x14c02000 0x0 0x1000>; + ranges = <0x0 0x0 0x0 0x14c02000 0x0 0x1000>; + #address-cells = <2>; + #size-cells = <2>; + #clock-cells = <1>; + #reset-cells = <1>; + + soc1_rst: reset-controller@200 { + #reset-cells = <1>; + }; + + soc1_clk: clock-controller@240 { + reg = <0 0x240 0 0x1c0>; + }; + }; + + uart12: serial@14c33b00 { + compatible = "ns16550a"; + reg = <0x0 0x14c33b00 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART12CLK>; + no-loopback-test; + pinctrl-names = "default"; + }; + }; +}; +