From patchwork Mon Jul 29 04:36:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 13744350 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 24D58C3DA61 for ; Mon, 29 Jul 2024 04:37:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=TGusBeF6LtGHCnC9cQ9CGXXLuABKto12QSnxBM8dUJE=; b=xODV9u7b11M+rQz/9Y+obMssoX KSmq8iThOJDe0BO1R3T83wWwcFexGwmLLiIYK8kJQO8XVxWNP3mJCI1M0PXfuXUMPCgOtsqVwJJm0 Lk8S3XKLb7qT7WhVBQkSXc/0sfFXrNqEgMmqlzOlQCwnoeF4fmcIo90nn/5iJ7KvudAkEzkuZ0Vba gwwVL6v7LtMyZtIKqXmN6cwCfLDt2uLJ7Bjx1vUBnIAbhRRiunw2gKrIUvD32ZJHC8UnzjpjeNljk tw7fRhi0yTHFpMEMvn7R8Qptohefb+qVMXmZ2JNXglLBydqcT7g9VLL3f+TnUoe+w5tYPjpaN9U2Y 95VIfIig==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYI8f-00000009y6Z-0DE1; Mon, 29 Jul 2024 04:37:37 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYI7W-00000009xqv-15Kg for linux-arm-kernel@lists.infradead.org; Mon, 29 Jul 2024 04:36:27 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 64221FEC; Sun, 28 Jul 2024 21:36:51 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.41.10]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 62F9E3F5A1; Sun, 28 Jul 2024 21:36:24 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: mark.rutland@arm.com, Anshuman Khandual Subject: [PATCH V2 2/3] aarch64: Enable access into 128 bit system registers from EL2 and below Date: Mon, 29 Jul 2024 10:06:05 +0530 Message-Id: <20240729043606.871451-3-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729043606.871451-1-anshuman.khandual@arm.com> References: <20240729043606.871451-1-anshuman.khandual@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240728_213626_358056_F6ADF46D X-CRM114-Status: UNSURE ( 8.36 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org FEAT_D128 adds 128 bit system registers like PAR_EL1, TTBR0_EL1, TTBR1_EL1, TTBR0_EL2, TTBR1_EL2, TTBR0_EL12, TTBR1_EL12 , VTTBR_EL2, RCWMASK_EL1, and RCWSMASK_EL1. But access into these register from EL2 and below trap to EL3 unless SCR_EL3.D128En is set. Enable access to 128 bit registers when they are implemented. Signed-off-by: Anshuman Khandual --- arch/aarch64/include/asm/cpu.h | 2 ++ arch/aarch64/init.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 85e735b..57c9cf2 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -61,6 +61,7 @@ #define SCR_EL3_TCR2EN BIT(43) #define SCR_EL3_SCTLR2En BIT(44) #define SCR_EL3_PIEN BIT(45) +#define SCR_EL3_D128En BIT(47) #define HCR_EL2_RES1 BIT(1) @@ -90,6 +91,7 @@ #define ID_AA64MMFR3_EL1_S2PIE BITS(15, 12) #define ID_AA64MMFR3_EL1_S1POE BITS(19, 16) #define ID_AA64MMFR3_EL1_S2POE BITS(23, 20) +#define ID_AA64MMFR3_EL1_D128 BITS(35, 32) #define ID_AA64PFR1_EL1_MTE BITS(11, 8) #define ID_AA64PFR1_EL1_SME BITS(27, 24) diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index fc0d2e3..afe4398 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -95,6 +95,9 @@ void cpu_init_el3(void) msr(SCTLR2_EL1, 0); } + if (mrs_field(ID_AA64MMFR3_EL1, D128)) + scr |= SCR_EL3_D128En; + msr(SCR_EL3, scr); msr(CPTR_EL3, cptr);