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[V2,3/3] aarch64: Enable access into RCW[S]MASK_EL1 registers from EL2 and below

Message ID 20240729043606.871451-4-anshuman.khandual@arm.com (mailing list archive)
State New, archived
Headers show
Series aarch64: Enable access for FEAT_D128 registers in EL1/EL2 | expand

Commit Message

Anshuman Khandual July 29, 2024, 4:36 a.m. UTC 
FEAT_THE adds RCW[S]MASK_EL1 system registers. But access into these system
registers from EL2 and below trap to EL3 unless SCR_EL3.RCWMASKEn is set.

Enable access to RCW[S]MASK_EL1 registers when they are implemented.

Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/aarch64/include/asm/cpu.h | 2 ++
 arch/aarch64/init.c            | 3 +++
 2 files changed, 5 insertions(+)
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Patch

diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index 57c9cf2..a5744e1 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -58,6 +58,7 @@ 
 #define SCR_EL3_TME			BIT(34)
 #define SCR_EL3_HXEn			BIT(38)
 #define SCR_EL3_EnTP2			BIT(41)
+#define SCR_EL3_RCWMASKEn		BIT(42)
 #define SCR_EL3_TCR2EN			BIT(43)
 #define SCR_EL3_SCTLR2En		BIT(44)
 #define SCR_EL3_PIEN			BIT(45)
@@ -95,6 +96,7 @@ 
 
 #define ID_AA64PFR1_EL1_MTE		BITS(11, 8)
 #define ID_AA64PFR1_EL1_SME		BITS(27, 24)
+#define ID_AA64PFR1_EL1_THE		BITS(51, 48)
 #define ID_AA64PFR0_EL1_SVE		BITS(35, 32)
 
 #define ID_AA64SMFR0_EL1		s3_0_c0_c4_5
diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
index afe4398..c9fc7f1 100644
--- a/arch/aarch64/init.c
+++ b/arch/aarch64/init.c
@@ -98,6 +98,9 @@  void cpu_init_el3(void)
 	if (mrs_field(ID_AA64MMFR3_EL1, D128))
 		scr |= SCR_EL3_D128En;
 
+	if (mrs_field(ID_AA64PFR1_EL1, THE))
+		scr |= SCR_EL3_RCWMASKEn;
+
 	msr(SCR_EL3, scr);
 
 	msr(CPTR_EL3, cptr);