From patchwork Mon Jul 29 04:36:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 13744352 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 555CBC3DA61 for ; Mon, 29 Jul 2024 04:38:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ir0KrKtFDnYdaNLyrc2AzA7p9ozrLQFQ9U0cM1NOtPI=; b=J2BKY5O3/L/SBt/BF/z9ApP7SE kMVfmbMZ0P4PhgsNwOp6r1UcoX1rD9UjDrLSjUWLMuL3++k6h9S8mW2y6L7AjFWLbfJstw87qLRD6 HBYjSgr2ie2AbkfHlerTlMxPIrf295MulKZrfrYgu1qn6mEezf6PBA6h8TOYWAuQPvBoeM1mL3d85 PY+vnYPhwYl/ZdLyDktRgduPihNWNC+n2NdFW4nr7PGv8WbP7C1zHYPAMq7kdaeGfmZyhW3NuGW/J 9JnR7QD1R2GyLWkY1EvBI4odwquOVS8+t645K2E+qCxmNnjzRS+cD1Kh9DQCDchvhfeD9xmmCu6yM mbj3hkTg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYI93-00000009yGZ-1IQ6; Mon, 29 Jul 2024 04:38:01 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYI7a-00000009xsq-3eb1 for linux-arm-kernel@lists.infradead.org; Mon, 29 Jul 2024 04:36:32 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 56B571007; Sun, 28 Jul 2024 21:36:53 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.41.10]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6E87D3F5A1; Sun, 28 Jul 2024 21:36:26 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: mark.rutland@arm.com, Anshuman Khandual Subject: [PATCH V2 3/3] aarch64: Enable access into RCW[S]MASK_EL1 registers from EL2 and below Date: Mon, 29 Jul 2024 10:06:06 +0530 Message-Id: <20240729043606.871451-4-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729043606.871451-1-anshuman.khandual@arm.com> References: <20240729043606.871451-1-anshuman.khandual@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240728_213630_971187_06B7DEF3 X-CRM114-Status: UNSURE ( 8.36 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org FEAT_THE adds RCW[S]MASK_EL1 system registers. But access into these system registers from EL2 and below trap to EL3 unless SCR_EL3.RCWMASKEn is set. Enable access to RCW[S]MASK_EL1 registers when they are implemented. Signed-off-by: Anshuman Khandual --- arch/aarch64/include/asm/cpu.h | 2 ++ arch/aarch64/init.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 57c9cf2..a5744e1 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -58,6 +58,7 @@ #define SCR_EL3_TME BIT(34) #define SCR_EL3_HXEn BIT(38) #define SCR_EL3_EnTP2 BIT(41) +#define SCR_EL3_RCWMASKEn BIT(42) #define SCR_EL3_TCR2EN BIT(43) #define SCR_EL3_SCTLR2En BIT(44) #define SCR_EL3_PIEN BIT(45) @@ -95,6 +96,7 @@ #define ID_AA64PFR1_EL1_MTE BITS(11, 8) #define ID_AA64PFR1_EL1_SME BITS(27, 24) +#define ID_AA64PFR1_EL1_THE BITS(51, 48) #define ID_AA64PFR0_EL1_SVE BITS(35, 32) #define ID_AA64SMFR0_EL1 s3_0_c0_c4_5 diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index afe4398..c9fc7f1 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -98,6 +98,9 @@ void cpu_init_el3(void) if (mrs_field(ID_AA64MMFR3_EL1, D128)) scr |= SCR_EL3_D128En; + if (mrs_field(ID_AA64PFR1_EL1, THE)) + scr |= SCR_EL3_RCWMASKEn; + msr(SCR_EL3, scr); msr(CPTR_EL3, cptr);