diff mbox series

[1/5] dt-bindings: clock: mt6765: Add missing PMIC clock

Message ID 20240729073428.28983-2-me@adomerle.xyz (mailing list archive)
State New, archived
Headers show
Series Initial preparations for MT6765 | expand

Commit Message

Arseniy Velikanov July 29, 2024, 7:34 a.m. UTC 
Add PWRAP clock binding and shift the following ones

Fixes: eb7beb65ac30 ("clk: mediatek: add mt6765 clock IDs")
Signed-off-by: Arseniy Velikanov <me@adomerle.xyz>
---
 include/dt-bindings/clock/mt6765-clk.h | 131 +++++++++++++------------
 1 file changed, 66 insertions(+), 65 deletions(-)

Comments

Krzysztof Kozlowski July 29, 2024, 7:36 a.m. UTC | #1 
On 29/07/2024 09:34, Arseniy Velikanov wrote:
> Add PWRAP clock binding and shift the following ones
> 
> Fixes: eb7beb65ac30 ("clk: mediatek: add mt6765 clock IDs")

Please describe the bug and its observable impact.

> Signed-off-by: Arseniy Velikanov <me@adomerle.xyz>
> ---
>  include/dt-bindings/clock/mt6765-clk.h | 131 +++++++++++++------------
>  1 file changed, 66 insertions(+), 65 deletions(-)
> 
> diff --git a/include/dt-bindings/clock/mt6765-clk.h b/include/dt-bindings/clock/mt6765-clk.h
> index eb97e568518e..5d3a603a0d36 100644
> --- a/include/dt-bindings/clock/mt6765-clk.h
> +++ b/include/dt-bindings/clock/mt6765-clk.h
> @@ -161,71 +161,72 @@
>  #define CLK_TOP_NR_CLK			126
>  
>  /* INFRACFG */
> -#define CLK_IFR_ICUSB			0

NAK, you cannot change the bindings. Especially without bigger
description where the bug is.

Best regards,
Krzysztof
AngeloGioacchino Del Regno July 29, 2024, 7:46 a.m. UTC | #2 
Il 29/07/24 09:34, Arseniy Velikanov ha scritto:
> Add PWRAP clock binding and shift the following ones
> 
> Fixes: eb7beb65ac30 ("clk: mediatek: add mt6765 clock IDs")
> Signed-off-by: Arseniy Velikanov <me@adomerle.xyz>

Hello,

sorry, this breaks ABI. Please put the new clock at the end of the list
instead of putting it at the beginning.

Also, since mt6765 has no devicetrees upstream, technically this SoC was never
used by anything... so you can (please) avoid putting Fixes tag for this one.

Thanks,
Angelo

> ---
>   include/dt-bindings/clock/mt6765-clk.h | 131 +++++++++++++------------
>   1 file changed, 66 insertions(+), 65 deletions(-)
>
diff mbox series

Patch

diff --git a/include/dt-bindings/clock/mt6765-clk.h b/include/dt-bindings/clock/mt6765-clk.h
index eb97e568518e..5d3a603a0d36 100644
--- a/include/dt-bindings/clock/mt6765-clk.h
+++ b/include/dt-bindings/clock/mt6765-clk.h
@@ -161,71 +161,72 @@ 
 #define CLK_TOP_NR_CLK			126
 
 /* INFRACFG */
-#define CLK_IFR_ICUSB			0
-#define CLK_IFR_GCE			1
-#define CLK_IFR_THERM			2
-#define CLK_IFR_I2C_AP			3
-#define CLK_IFR_I2C_CCU			4
-#define CLK_IFR_I2C_SSPM		5
-#define CLK_IFR_I2C_RSV			6
-#define CLK_IFR_PWM_HCLK		7
-#define CLK_IFR_PWM1			8
-#define CLK_IFR_PWM2			9
-#define CLK_IFR_PWM3			10
-#define CLK_IFR_PWM4			11
-#define CLK_IFR_PWM5			12
-#define CLK_IFR_PWM			13
-#define CLK_IFR_UART0			14
-#define CLK_IFR_UART1			15
-#define CLK_IFR_GCE_26M			16
-#define CLK_IFR_CQ_DMA_FPC		17
-#define CLK_IFR_BTIF			18
-#define CLK_IFR_SPI0			19
-#define CLK_IFR_MSDC0			20
-#define CLK_IFR_MSDC1			21
-#define CLK_IFR_TRNG			22
-#define CLK_IFR_AUXADC			23
-#define CLK_IFR_CCIF1_AP		24
-#define CLK_IFR_CCIF1_MD		25
-#define CLK_IFR_AUXADC_MD		26
-#define CLK_IFR_AP_DMA			27
-#define CLK_IFR_DEVICE_APC		28
-#define CLK_IFR_CCIF_AP			29
-#define CLK_IFR_AUDIO			30
-#define CLK_IFR_CCIF_MD			31
-#define CLK_IFR_RG_PWM_FBCLK6		32
-#define CLK_IFR_DISP_PWM		33
-#define CLK_IFR_CLDMA_BCLK		34
-#define CLK_IFR_AUDIO_26M_BCLK		35
-#define CLK_IFR_SPI1			36
-#define CLK_IFR_I2C4			37
-#define CLK_IFR_SPI2			38
-#define CLK_IFR_SPI3			39
-#define CLK_IFR_I2C5			40
-#define CLK_IFR_I2C5_ARBITER		41
-#define CLK_IFR_I2C5_IMM		42
-#define CLK_IFR_I2C1_ARBITER		43
-#define CLK_IFR_I2C1_IMM		44
-#define CLK_IFR_I2C2_ARBITER		45
-#define CLK_IFR_I2C2_IMM		46
-#define CLK_IFR_SPI4			47
-#define CLK_IFR_SPI5			48
-#define CLK_IFR_CQ_DMA			49
-#define CLK_IFR_FAES_FDE		50
-#define CLK_IFR_MSDC0_SELF		51
-#define CLK_IFR_MSDC1_SELF		52
-#define CLK_IFR_I2C6			53
-#define CLK_IFR_AP_MSDC0		54
-#define CLK_IFR_MD_MSDC0		55
-#define CLK_IFR_MSDC0_SRC		56
-#define CLK_IFR_MSDC1_SRC		57
-#define CLK_IFR_AES_TOP0_BCLK		58
-#define CLK_IFR_MCU_PM_BCLK		59
-#define CLK_IFR_CCIF2_AP		60
-#define CLK_IFR_CCIF2_MD		61
-#define CLK_IFR_CCIF3_AP		62
-#define CLK_IFR_CCIF3_MD		63
-#define CLK_IFR_NR_CLK			64
+#define CLK_IFR_PMIC_AP			0
+#define CLK_IFR_ICUSB			1
+#define CLK_IFR_GCE			2
+#define CLK_IFR_THERM			3
+#define CLK_IFR_I2C_AP			4
+#define CLK_IFR_I2C_CCU			5
+#define CLK_IFR_I2C_SSPM		6
+#define CLK_IFR_I2C_RSV			7
+#define CLK_IFR_PWM_HCLK		8
+#define CLK_IFR_PWM1			9
+#define CLK_IFR_PWM2			10
+#define CLK_IFR_PWM3			11
+#define CLK_IFR_PWM4			12
+#define CLK_IFR_PWM5			13
+#define CLK_IFR_PWM			14
+#define CLK_IFR_UART0			15
+#define CLK_IFR_UART1			16
+#define CLK_IFR_GCE_26M			17
+#define CLK_IFR_CQ_DMA_FPC		18
+#define CLK_IFR_BTIF			19
+#define CLK_IFR_SPI0			20
+#define CLK_IFR_MSDC0			21
+#define CLK_IFR_MSDC1			22
+#define CLK_IFR_TRNG			23
+#define CLK_IFR_AUXADC			24
+#define CLK_IFR_CCIF1_AP		25
+#define CLK_IFR_CCIF1_MD		26
+#define CLK_IFR_AUXADC_MD		27
+#define CLK_IFR_AP_DMA			28
+#define CLK_IFR_DEVICE_APC		29
+#define CLK_IFR_CCIF_AP			30
+#define CLK_IFR_AUDIO			31
+#define CLK_IFR_CCIF_MD			32
+#define CLK_IFR_RG_PWM_FBCLK6		33
+#define CLK_IFR_DISP_PWM		34
+#define CLK_IFR_CLDMA_BCLK		35
+#define CLK_IFR_AUDIO_26M_BCLK		36
+#define CLK_IFR_SPI1			37
+#define CLK_IFR_I2C4			38
+#define CLK_IFR_SPI2			39
+#define CLK_IFR_SPI3			40
+#define CLK_IFR_I2C5			41
+#define CLK_IFR_I2C5_ARBITER		42
+#define CLK_IFR_I2C5_IMM		43
+#define CLK_IFR_I2C1_ARBITER		44
+#define CLK_IFR_I2C1_IMM		45
+#define CLK_IFR_I2C2_ARBITER		46
+#define CLK_IFR_I2C2_IMM		47
+#define CLK_IFR_SPI4			48
+#define CLK_IFR_SPI5			49
+#define CLK_IFR_CQ_DMA			50
+#define CLK_IFR_FAES_FDE		51
+#define CLK_IFR_MSDC0_SELF		52
+#define CLK_IFR_MSDC1_SELF		53
+#define CLK_IFR_I2C6			54
+#define CLK_IFR_AP_MSDC0		55
+#define CLK_IFR_MD_MSDC0		56
+#define CLK_IFR_MSDC0_SRC		57
+#define CLK_IFR_MSDC1_SRC		58
+#define CLK_IFR_AES_TOP0_BCLK		59
+#define CLK_IFR_MCU_PM_BCLK		60
+#define CLK_IFR_CCIF2_AP		61
+#define CLK_IFR_CCIF2_MD		62
+#define CLK_IFR_CCIF3_AP		63
+#define CLK_IFR_CCIF3_MD		64
+#define CLK_IFR_NR_CLK			65
 
 /* AUDIO */
 #define CLK_AUDIO_AFE			0