diff mbox series

[v1,1/2] ARM: dts: samsung: Add cache information to the Exynos4412 SoCS

Message ID 20240730091322.5741-1-linux.amoon@gmail.com (mailing list archive)
State New, archived
Headers show
Series [v1,1/2] ARM: dts: samsung: Add cache information to the Exynos4412 SoCS | expand

Commit Message

Anand Moon July 30, 2024, 9:13 a.m. UTC 
As per the Exynos 4412 user manaual add missing cache information to
the Exynos 4412 SoC.

- Each Cortex-A9 core has 32KB of L1 instruction cache available and
	32KB of L1 data cache available.
- Along with 1M unified L2 cache.

Features of ARM Cortex-A9
- Optimized L1 caches for system performance and power.
- Integrated 1 MB L2 Cache using standard compiled RAMs.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 arch/arm/boot/dts/samsung/exynos4412.dtsi | 37 +++++++++++++++++++++++
 1 file changed, 37 insertions(+)


base-commit: dc1c8034e31b14a2e5e212104ec508aec44ce1b9
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/samsung/exynos4412.dtsi b/arch/arm/boot/dts/samsung/exynos4412.dtsi
index dcbe0ce6180f..d133c8a8e8d4 100644
--- a/arch/arm/boot/dts/samsung/exynos4412.dtsi
+++ b/arch/arm/boot/dts/samsung/exynos4412.dtsi
@@ -48,6 +48,13 @@  cpu0: cpu@a00 {
 			clock-names = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu1: cpu@a01 {
@@ -58,6 +65,13 @@  cpu1: cpu@a01 {
 			clock-names = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu2: cpu@a02 {
@@ -68,6 +82,13 @@  cpu2: cpu@a02 {
 			clock-names = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu3: cpu@a03 {
@@ -78,6 +99,22 @@  cpu3: cpu@a03 {
 			clock-names = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&L2>;
+		};
+
+		L2: l2-cache {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
+			cache-size = <0x100000>; /* L2, 1M */
+			cache-line-size = <64>;
+			cache-sets = <512>;
 		};
 	};