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Wed, 31 Jul 2024 12:10:46 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 46VHAVgQ036362; Wed, 31 Jul 2024 12:10:43 -0500 From: Manorit Chawdhry Date: Wed, 31 Jul 2024 22:40:29 +0530 Subject: [PATCH v3 3/9] arm64: dts: ti: Split k3-j784s4-j742s2-common.dtsi MIME-Version: 1.0 Message-ID: <20240731-b4-upstream-j742s2-v3-3-da7fe3aa9e90@ti.com> References: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> In-Reply-To: <20240731-b4-upstream-j742s2-v3-0-da7fe3aa9e90@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Udit Kumar , Neha Malcom Francis , Aniket Limaye , Manorit Chawdhry X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1722445831; l=8025; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=tiZgpMVSYamgxzdjCpc1ORHBAdASeolJLopA9GJxS7g=; b=qmaSfh25Oo0U+Y9xZrOuwl2vqpnHEq0aCMZ81ehmr0q2sG4MHm+vVlcn1emRY/2BavouiLa2a uTQE6rqQRzoBgq3O8vVbViBM8VJeIEVZ8BNmZh0+FC3eyLTc58bL5I2 X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240731_101050_735554_20604DDC X-CRM114-Status: GOOD ( 11.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org k3-j784s4-j742s2-common.dtsi will be included in k3-j742s2.dtsi at a later point so move j784s4 related stuff to k3-j784s4.dtsi Signed-off-by: Manorit Chawdhry --- .../arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi | 156 -------------------- arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 158 +++++++++++++++++++++ 2 files changed, 158 insertions(+), 156 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi index 76e43ee44496..958054ab1018 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi @@ -15,166 +15,10 @@ #include "k3-pinctrl.h" / { - model = "Texas Instruments K3 J784S4 SoC"; - compatible = "ti,j784s4"; interrupt-parent = <&gic500>; #address-cells = <2>; #size-cells = <2>; - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu-map { - cluster0: cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - - core2 { - cpu = <&cpu2>; - }; - - core3 { - cpu = <&cpu3>; - }; - }; - - cluster1: cluster1 { - core0 { - cpu = <&cpu4>; - }; - - core1 { - cpu = <&cpu5>; - }; - - core2 { - cpu = <&cpu6>; - }; - - core3 { - cpu = <&cpu7>; - }; - }; - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a72"; - reg = <0x000>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a72"; - reg = <0x001>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a72"; - reg = <0x002>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a72"; - reg = <0x003>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - - cpu4: cpu@100 { - compatible = "arm,cortex-a72"; - reg = <0x100>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_1>; - }; - - cpu5: cpu@101 { - compatible = "arm,cortex-a72"; - reg = <0x101>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_1>; - }; - - cpu6: cpu@102 { - compatible = "arm,cortex-a72"; - reg = <0x102>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_1>; - }; - - cpu7: cpu@103 { - compatible = "arm,cortex-a72"; - reg = <0x103>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_1>; - }; - }; - L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi index 46cff5ed3730..16ade4fd9cbd 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi @@ -10,3 +10,161 @@ #include "k3-j784s4-j742s2-common.dtsi" +/ { + model = "Texas Instruments K3 J784S4 SoC"; + compatible = "ti,j784s4"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1: cluster1 { + core0 { + cpu = <&cpu4>; + }; + + core1 { + cpu = <&cpu5>; + }; + + core2 { + cpu = <&cpu6>; + }; + + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a72"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a72"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_0>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a72"; + reg = <0x002>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_0>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a72"; + reg = <0x003>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_0>; + }; + + cpu4: cpu@100 { + compatible = "arm,cortex-a72"; + reg = <0x100>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_1>; + }; + + cpu5: cpu@101 { + compatible = "arm,cortex-a72"; + reg = <0x101>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_1>; + }; + + cpu6: cpu@102 { + compatible = "arm,cortex-a72"; + reg = <0x102>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_1>; + }; + + cpu7: cpu@103 { + compatible = "arm,cortex-a72"; + reg = <0x103>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&L2_1>; + }; + }; +};