From patchwork Thu Aug 1 05:44:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 13749603 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7A89CC3DA4A for ; Thu, 1 Aug 2024 05:45:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=s84zZJfZbEU/O9h6LjajAuZqfRIZPKVub146VOqnL5o=; b=JLSssw7H+NkD/Q8JBi9ihp+YF0 DmGbyA+N9sf0kvLMV8fLyeFQKiOqck+5guaZX1OLmPrlX2lMPHe5xMYygvdo6X553BPdaZCWoSdfl 5awPXbWFBf/EQhasFwoU8haNQYFGWI5O2Qd1Qw0KrE603pfqdujwJ4oRlf2gqnW7rk8krIAByrVfH 8IKJRvig75+KBANtwWVdVIYdEShbZ55/zs3ObZlXOaAwxOLm+evwsc1SrduX9HtwBrq9j/ljtHQLQ 6rAIw4vBujciqFKMdFJIYMSw12si+HNf363ZjzfoGq0RwUzKooc2LdxTP3tvTRbbda7USGqxduUuw lm1fU1lg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZOdE-00000003nyY-2Ht2; Thu, 01 Aug 2024 05:45:44 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZOcL-00000003nom-36yL for linux-arm-kernel@lists.infradead.org; Thu, 01 Aug 2024 05:44:51 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C08351063; Wed, 31 Jul 2024 22:45:12 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.56.112]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id CE2443F5A1; Wed, 31 Jul 2024 22:44:44 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Mark Brown , linux-kernel@vger.kernel.org Subject: [PATCH 1/1] arm64/tools/sysreg: Add Sysreg128/SysregFields128 Date: Thu, 1 Aug 2024 11:14:36 +0530 Message-Id: <20240801054436.612024-2-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240801054436.612024-1-anshuman.khandual@arm.com> References: <20240801054436.612024-1-anshuman.khandual@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240731_224449_892808_34137838 X-CRM114-Status: GOOD ( 13.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org FEAT_SYSREG128 enables 128 bit wide system registers which also need to be defined in (arch/arm64/toos/sysreg) for auto mask generation. This adds two new field types i.e Sysreg128 and SysregFields128 for that same purpose. It utilizes recently added macro GENMASK_U128() while also adding some helpers such as define_field_128() and parse_bitdef_128(). Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/gen-sysreg.awk | 231 ++++++++++++++++++++++++++++++++ 1 file changed, 231 insertions(+) diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.awk index d1254a056114..a1571881d1c3 100755 --- a/arch/arm64/tools/gen-sysreg.awk +++ b/arch/arm64/tools/gen-sysreg.awk @@ -56,6 +56,13 @@ function define_field(reg, field, msb, lsb) { define(reg "_" field "_WIDTH", msb - lsb + 1) } +function define_field_128(reg, field, msb, lsb) { + define(reg "_" field, "GENMASK_U128(" msb ", " lsb ")") + define(reg "_" field "_MASK", "GENMASK_U128(" msb ", " lsb ")") + define(reg "_" field "_SHIFT", lsb) + define(reg "_" field "_WIDTH", msb - lsb + 1) +} + # Print a field _SIGNED definition for a field function define_field_sign(reg, field, sign) { define(reg "_" field "_SIGNED", sign) @@ -89,6 +96,33 @@ function parse_bitdef(reg, field, bitdef, _bits) next_bit = lsb - 1 } +function parse_bitdef_128(reg, field, bitdef, _bits) +{ + if (bitdef ~ /^[0-9]+$/) { + msb = bitdef + lsb = bitdef + } else if (split(bitdef, _bits, ":") == 2) { + msb = _bits[1] + lsb = _bits[2] + } else { + fatal("invalid bit-range definition '" bitdef "'") + } + + + if (msb != next_bit) + fatal(reg "." field " starts at " msb " not " next_bit) + if (127 < msb || msb < 0) + fatal(reg "." field " invalid high bit in '" bitdef "'") + if (127 < lsb || lsb < 0) + fatal(reg "." field " invalid low bit in '" bitdef "'") + if (msb < lsb) + fatal(reg "." field " invalid bit-range '" bitdef "'") + if (low > high) + fatal(reg "." field " has invalid range " high "-" low) + + next_bit = lsb - 1 +} + BEGIN { print "#ifndef __ASM_SYSREG_DEFS_H" print "#define __ASM_SYSREG_DEFS_H" @@ -111,6 +145,99 @@ END { /^$/ { next } /^[\t ]*#/ { next } +/^SysregFields128/ && block_current() == "Root" { + block_push("SysregFields128") + + expect_fields(2) + + reg = $2 + + res0 = "UL(0)" + res1 = "UL(0)" + unkn = "UL(0)" + + next_bit = 127 + + next +} + +/^EndSysregFields128/ && block_current() == "SysregFields128" { + if (next_bit > 0) + fatal("Unspecified bits in " reg) + + define(reg "_RES0", "(" res0 ")") + define(reg "_RES1", "(" res1 ")") + define(reg "_UNKN", "(" unkn ")") + print "" + + reg = null + res0 = null + res1 = null + unkn = null + + block_pop() + next +} + +/^Sysreg128/ && block_current() == "Root" { + block_push("Sysreg128") + + expect_fields(7) + + reg = $2 + op0 = $3 + op1 = $4 + crn = $5 + crm = $6 + op2 = $7 + + res0 = "UL(0)" + res1 = "UL(0)" + unkn = "UL(0)" + + define("REG_" reg, "S" op0 "_" op1 "_C" crn "_C" crm "_" op2) + define("SYS_" reg, "sys_reg(" op0 ", " op1 ", " crn ", " crm ", " op2 ")") + + define("SYS_" reg "_Op0", op0) + define("SYS_" reg "_Op1", op1) + define("SYS_" reg "_CRn", crn) + define("SYS_" reg "_CRm", crm) + define("SYS_" reg "_Op2", op2) + + print "" + + next_bit = 127 + + next +} + +/^EndSysreg128/ && block_current() == "Sysreg128" { + if (next_bit > 0) + fatal("Unspecified bits in " reg) + + if (res0 != null) + define(reg "_RES0", "(" res0 ")") + if (res1 != null) + define(reg "_RES1", "(" res1 ")") + if (unkn != null) + define(reg "_UNKN", "(" unkn ")") + if (res0 != null || res1 != null || unkn != null) + print "" + + reg = null + op0 = null + op1 = null + crn = null + crm = null + op2 = null + res0 = null + res1 = null + unkn = null + + block_pop() + next +} + /^SysregFields/ && block_current() == "Root" { block_push("SysregFields") @@ -223,6 +350,22 @@ END { next } +/^Fields/ && block_current() == "Sysreg128" { + expect_fields(2) + + if (next_bit != 127) + fatal("Some fields already defined for " reg) + + print "/* For " reg " fields see " $2 " */" + print "" + + next_bit = 0 + res0 = null + res1 = null + unkn = null + + next +} /^Res0/ && (block_current() == "Sysreg" || block_current() == "SysregFields") { expect_fields(2) @@ -234,6 +377,16 @@ END { next } +/^Res0/ && (block_current() == "Sysreg128" || block_current() == "SysregFields128") { + expect_fields(2) + parse_bitdef_128(reg, "RES0", $2) + field = "RES0_" msb "_" lsb + + res0 = res0 " | GENMASK_U128(" msb ", " lsb ")" + + next +} + /^Res1/ && (block_current() == "Sysreg" || block_current() == "SysregFields") { expect_fields(2) parse_bitdef(reg, "RES1", $2) @@ -244,6 +397,16 @@ END { next } +/^Res1/ && (block_current() == "Sysreg128" || block_current() == "SysregFields128") { + expect_fields(2) + parse_bitdef_128(reg, "RES1", $2) + field = "RES1_" msb "_" lsb + + res1 = res1 " | GENMASK_U128(" msb ", " lsb ")" + + next +} + /^Unkn/ && (block_current() == "Sysreg" || block_current() == "SysregFields") { expect_fields(2) parse_bitdef(reg, "UNKN", $2) @@ -254,6 +417,16 @@ END { next } +/^Unkn/ && (block_current() == "Sysreg128" || block_current() == "SysregFields128") { + expect_fields(2) + parse_bitdef_128(reg, "UNKN", $2) + field = "UNKN_" msb "_" lsb + + unkn = unkn " | GENMASK_U128(" msb ", " lsb ")" + + next +} + /^Field/ && (block_current() == "Sysreg" || block_current() == "SysregFields") { expect_fields(3) field = $3 @@ -265,6 +438,17 @@ END { next } +/^Field/ && (block_current() == "Sysreg128" || block_current() == "SysregFields128") { + expect_fields(3) + field = $3 + parse_bitdef_128(reg, field, $2) + + define_field_128(reg, field, msb, lsb) + print "" + + next +} + /^Raz/ && (block_current() == "Sysreg" || block_current() == "SysregFields") { expect_fields(2) parse_bitdef(reg, field, $2) @@ -272,6 +456,14 @@ END { next } +/^Raz/ && (block_current() == "Sysreg128" || block_current() == "SysregFields128") { + expect_fields(2) + parse_bitdef_128(reg, field, $2) + + next +} + + /^SignedEnum/ && (block_current() == "Sysreg" || block_current() == "SysregFields") { block_push("Enum") @@ -285,6 +477,19 @@ END { next } +/^SignedEnum/ && (block_current() == "Sysreg128" || block_current() == "SysregFields128") { + block_push("Enum") + + expect_fields(3) + field = $3 + parse_bitdef_128(reg, field, $2) + + define_field_128(reg, field, msb, lsb) + define_field_sign(reg, field, "true") + + next +} + /^UnsignedEnum/ && (block_current() == "Sysreg" || block_current() == "SysregFields") { block_push("Enum") @@ -298,6 +503,20 @@ END { next } +/^UnsignedEnum/ && (block_current() == "Sysreg128" || block_current() == "SysregFields128") { + block_push("Enum") + + expect_fields(3) + field = $3 + parse_bitdef_128(reg, field, $2) + + define_field_128(reg, field, msb, lsb) + define_field_sign(reg, field, "false") + + next +} + + /^Enum/ && (block_current() == "Sysreg" || block_current() == "SysregFields") { block_push("Enum") @@ -310,6 +529,18 @@ END { next } +/^Enum/ && (block_current() == "Sysreg128" || block_current() == "SysregFields128") { + block_push("Enum") + + expect_fields(3) + field = $3 + parse_bitdef_128(reg, field, $2) + + define_field_128(reg, field, msb, lsb) + + next +} + /^EndEnum/ && block_current() == "Enum" { field = null