From patchwork Fri Aug 2 21:06:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Hilman X-Patchwork-Id: 13752003 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F341CC3DA4A for ; Fri, 2 Aug 2024 21:07:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=MsPDBFDSDGtTL2KXQ6qVY7dOAW5W1axnv1PXbOxRfbg=; b=SUKSOVaUv8nMMhUOnt3d/INgMn +vFHa9hMYVNhweChK8SXw9K8V+WFpF6Ln8u4Jm0xupxGX7/kDpnKguchvdPDZZ8yKQwkjHrQjQzE3 FrlDWaHoguvWlrbK0eRg2U1J+EDESS9OTq+HgdC7a+usXzKirwoc5yx7iolR5L64TgpXfAZdaSbc5 yBIkAEkM32A1NIdUDbx0qtOCHJeqJwXNQmZJWcIzV77VByTAMYAcjAQuqzQTT3/rJ7SZLxnSPcOPM PWzKUR+nHNv1NU8ZoGLuqigWBDYBBK5u/Q9tuWQRK2hs1SEl8/8zbXUOVudlpRn56gweYbAOFdzCJ HekDllZg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZzUa-0000000A4TQ-3tut; Fri, 02 Aug 2024 21:07:16 +0000 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sZzU5-0000000A4Ol-08cW for linux-arm-kernel@lists.infradead.org; Fri, 02 Aug 2024 21:06:47 +0000 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1ff4fa918afso18017895ad.1 for ; Fri, 02 Aug 2024 14:06:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1722632803; x=1723237603; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=MsPDBFDSDGtTL2KXQ6qVY7dOAW5W1axnv1PXbOxRfbg=; b=iv/+854XmMFbiME3r2Wa/RHgaBmOr7GI8OzWHCetU5/fJAUdK4mTO0vmISIjcD8uU9 MoZVCJQakEe/qIWAJu+nZgNNvhq7Q1GEwPW4muYYU/5ZZ2M13n42Dp5AZgZScyyIrKfb 82GuaKoNkFeJiEIkePJvXT2FFdJvBHph6UX1Jy9R35zXTjx0EX4nXro/+Dl0OoQqdnlm 6V7PYfgy4wiZLb3WhwmJ1EMhS75tbuy633XUHaiDKQqh+GdD1uuZxAIsZT4dlKbeOQdA JqnAWi3V94N9FYSZzkrO4z2ETRzYc9b0Sp3S8OjJFSBUNxkdPDyuFo2JLVoy+Vbd1wdC suLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1722632803; x=1723237603; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=MsPDBFDSDGtTL2KXQ6qVY7dOAW5W1axnv1PXbOxRfbg=; b=VbPR1oy31NNfpOM3kx8V43y0csl5ag8YCgTPAElSG2KfK5/qzUdYY1VJfBsg9D30Tj jm0wqJX8MDKjdxVOhgpblyF2X7X8RPDrXQBIdQtAW9cFFdMR41Cdxwia8yC7HqO0hwAg NArgWr+a9+8nkn4qWispsan1Fk82z50RU22hyKaF/uVCj3/s3449s8e4xmWXkmXd5nA5 ZaLcou7I0o6TGRBcB2Ix7nXAaPeZ3I2ZjH7lFrSmS/1lHw7MMcryaqU95SV5xPi5nzQY ooOH2UYZNeDdmhfdlo6xKtwJiyDvAYP/3tRTltXSWvQ/9mSyMq2xWvu4OWpJeByzqdOw bCGw== X-Gm-Message-State: AOJu0YwhzKBBSxWmL/JpD5Fs12QbsYHUUDavjEJKV1x2xm2732Tdn9Nq mSkkcoy63ERpkZS1JcFiN51j5A3ZcWCVbOokFkQLtjMVI2I/jXKKsJYUIzUYzK4= X-Google-Smtp-Source: AGHT+IEk+MyYQ3fBrl4l7itZmBATX+jOjtFMUtipugbS7KUgE3sPfKUT1apPEm7M18ZarXXll/qjRQ== X-Received: by 2002:a17:902:ecd2:b0:1fd:93d2:fb94 with SMTP id d9443c01a7336-1ff573cc1f2mr58142545ad.48.1722632803561; Fri, 02 Aug 2024 14:06:43 -0700 (PDT) Received: from localhost ([71.212.170.185]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ff5905c879sm21610365ad.148.2024.08.02.14.06.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Aug 2024 14:06:43 -0700 (PDT) From: Kevin Hilman To: Nishanth Menon , Tero Kristo , Santosh Shilimkar Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Akashdeep Kaur , Markus Schneider-Pargmann , Vibhore Vardhan , Dhruva Gole Subject: [PATCH] firmware: ti_sci: add CPU latency constraint management Date: Fri, 2 Aug 2024 14:06:42 -0700 Message-ID: <20240802210642.3366046-1-khilman@baylibre.com> X-Mailer: git-send-email 2.46.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240802_140645_251154_C0FCE303 X-CRM114-Status: GOOD ( 15.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org During system-wide suspend, check if any of the CPUs have PM QoS resume latency constraints set. If so, set TI SCI constraint. TI SCI has a single system-wide latency constraint, so use the max of any of the CPU latencies as the system-wide value. Note: DM firmware clears all constraints at resume time, so constraints need to be checked/updated/sent at each system suspend. Co-developed-by: Vibhore Vardhan Signed-off-by: Vibhore Vardhan Signed-off-by: Kevin Hilman Reviewed-by: Dhruva Gole Signed-off-by: Dhruva Gole --- Depends on the TI SCI series where support for the constraints APIs are added: https://lore.kernel.org/r/20240801195422.2296347-1-msp@baylibre.com drivers/firmware/ti_sci.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index c6544cc12417..a141e07e7864 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -9,6 +9,7 @@ #define pr_fmt(fmt) "%s: " fmt, __func__ #include +#include #include #include #include @@ -19,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -3640,8 +3642,26 @@ static int ti_sci_prepare_system_suspend(struct ti_sci_info *info) static int ti_sci_suspend(struct device *dev) { struct ti_sci_info *info = dev_get_drvdata(dev); + struct device *cpu_dev; + s32 val, cpu_lat = 0; int ret; + if (info->fw_caps & MSG_FLAG_CAPS_LPM_DM_MANAGED) { + for_each_possible_cpu(i) { + cpu_dev = get_cpu_device(i); + val = dev_pm_qos_read_value(cpu_dev, DEV_PM_QOS_RESUME_LATENCY); + if (val != PM_QOS_RESUME_LATENCY_NO_CONSTRAINT) + cpu_lat = max(cpu_lat, val); + } + if (cpu_lat && (cpu_lat != PM_QOS_RESUME_LATENCY_NO_CONSTRAINT)) { + dev_dbg(cpu_dev, "%s: sending max CPU latency=%u\n", __func__, cpu_lat); + ret = ti_sci_cmd_set_latency_constraint(&info->handle, + cpu_lat, TISCI_MSG_CONSTRAINT_SET); + if (ret) + return ret; + } + } + ret = ti_sci_prepare_system_suspend(info); if (ret) return ret;