@@ -3946,20 +3946,18 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
"gout_peric0_peric0_top0_pclk_9", "mout_peric0_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
21, 0, 0),
- /* Disabling this clock makes the system hang. Mark the clock as critical. */
GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0,
"gout_peric0_peric0_top1_ipclk_0", "dout_peric0_usi0_uart",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0,
- 21, CLK_IS_CRITICAL, 0),
+ 21, 0, 0),
GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2,
"gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2,
21, CLK_SET_RATE_PARENT, 0),
- /* Disabling this clock makes the system hang. Mark the clock as critical. */
GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0,
"gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0,
- 21, CLK_IS_CRITICAL, 0),
+ 21, 0, 0),
GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2,
"gout_peric0_peric0_top1_pclk_2", "mout_peric0_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2,
The peric0_top1_ipclk_0 and peric0_top1_pclk_0 are the clocks going to peric0/uart_usi, with pclk being the bus clock. Without pclk running, any bus access will hang. Unfortunately, in commit d97b6c902a40 ("arm64: dts: exynos: gs101: update USI UART to use peric0 clocks") the gs101 DT ended up specifying an incorrect pclk in the respective node and instead the two clocks here were marked as critical. As a side-effect and by accident, having them 'critical' also worked-around a problem where earlycon stops to work sometime into the boot for two reasons: * peric0_top1_ipclk_0 requires its parent gout_cmu_peric0_ip to be running, but because earlycon doesn't deal with clocks that parent will be disabled when none of the other drivers that actually deal with clocks correctly require it to be running and the real serial driver (which does deal with clocks) hasn't taken over yet * hand-over between earlycon and serial driver appears to be fragile and clocks get enabled and disabled a few times, which also causes register access to hang while earlycon is still active (A wordier explanation can also be found in [1]) Since then, the DT has been updated to use the correct clock in commit 21e4e8807bfc ("arm64: dts: exynos: gs101: use correct clocks for usi_uart"). Furthermore, the clk core now helps OF platforms with their stdout (earlycon) clocks during early boot and thereby avoids the problem described above. The driver here can now be corrected and the work-arounds removed. Do so. Link: https://lore.kernel.org/all/d45de3b2bb6b48653842cf1f74e58889ed6783ae.camel@linaro.org/ [1] Fixes: 893f133a040b ("clk: samsung: gs101: add support for cmu_peric0") Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> --- v5: update commit message v4: - the earlycon issue described in the commit message in previous versions of this patch is gone with "clk: samsung: gs101: allow earlycon to work unconditionally", so no need to mention anything v3: - add git commit SHA1s (Krzysztof) - add link to wordier description of earlycon issue v2: - commit message typo fixed - collect Reviewed-by: tags --- drivers/clk/samsung/clk-gs101.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)