| Message ID | 20240808-qcom_ipq_cmnpll-v1-3-b0631dcbf785@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add common PLL clock controller driver for IPQ9574 | expand |
On 08/08/2024 16:03, Luo Jie wrote: > The common PLL clock controller provides fixed rate output clocks to > the hardware blocks that enable ethernet function on IPQ platform. That's defconfig for all platforms, so how anyone can guess which one you target here? Be specific, which company, which Soc, which board needs it. Best regards, Krzysztof
On 8/8/2024 10:41 PM, Krzysztof Kozlowski wrote: > On 08/08/2024 16:03, Luo Jie wrote: >> The common PLL clock controller provides fixed rate output clocks to >> the hardware blocks that enable ethernet function on IPQ platform. > > That's defconfig for all platforms, so how anyone can guess which one > you target here? Be specific, which company, which Soc, which board > needs it. > Sure, I will update the commit message as below to provide the details required. The common PLL hardware block is available in the Qualcomm IPQ SoC such as IPQ9574 and IPQ5332. It provides fixed rate output clocks to Ethernet related hardware blocks such as external Ethernet PHY or switch. This driver is initially being enabled for IPQ9574. All boards based on IPQ9574 SoC will require to include this driver in the build. > > > Best regards, > Krzysztof >
On Fri, Aug 09, 2024 at 07:36:35PM +0800, Jie Luo wrote: > > > On 8/8/2024 10:41 PM, Krzysztof Kozlowski wrote: > > On 08/08/2024 16:03, Luo Jie wrote: > > > The common PLL clock controller provides fixed rate output clocks to > > > the hardware blocks that enable ethernet function on IPQ platform. > > > > That's defconfig for all platforms, so how anyone can guess which one > > you target here? Be specific, which company, which Soc, which board > > needs it. > > > > Sure, I will update the commit message as below to provide the details > required. > > The common PLL hardware block is available in the Qualcomm IPQ SoC such > as IPQ9574 and IPQ5332. It provides fixed rate output clocks to Ethernet > related hardware blocks such as external Ethernet PHY or switch. This > driver is initially being enabled for IPQ9574. All boards based on > IPQ9574 SoC will require to include this driver in the build. Does it provide more than Ethernet clocks? I'm just wondering why the name `common`, when it seems pretty uncommon, specialised for Ethernet clocks on a couple of SoCs. Andrew
On 8/9/2024 9:34 PM, Andrew Lunn wrote: > On Fri, Aug 09, 2024 at 07:36:35PM +0800, Jie Luo wrote: >> >> >> On 8/8/2024 10:41 PM, Krzysztof Kozlowski wrote: >>> On 08/08/2024 16:03, Luo Jie wrote: >>>> The common PLL clock controller provides fixed rate output clocks to >>>> the hardware blocks that enable ethernet function on IPQ platform. >>> >>> That's defconfig for all platforms, so how anyone can guess which one >>> you target here? Be specific, which company, which Soc, which board >>> needs it. >>> >> >> Sure, I will update the commit message as below to provide the details >> required. >> >> The common PLL hardware block is available in the Qualcomm IPQ SoC such >> as IPQ9574 and IPQ5332. It provides fixed rate output clocks to Ethernet >> related hardware blocks such as external Ethernet PHY or switch. This >> driver is initially being enabled for IPQ9574. All boards based on >> IPQ9574 SoC will require to include this driver in the build. > > Does it provide more than Ethernet clocks? I'm just wondering why the > name `common`, when it seems pretty uncommon, specialised for Ethernet > clocks on a couple of SoCs. > > Andrew No, this block does not provide any other functionality other than allowing this PLL to be configured for supplying clocks to Ethernet devices. The hardware programming guide names this block as the 'CMN' block, so we included the 'cmn' phrase in the driver namespace. However, I will update commit message to clarify that 'cmn' is the block name and it does not provide any other function other than enabling clocks to Ethernet related devices.
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 01dd286ba7ef..1bc7bd86e589 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1300,6 +1300,7 @@ CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_QCOM_CLK_RPMH=y CONFIG_IPQ_APSS_6018=y CONFIG_IPQ_APSS_5018=y +CONFIG_IPQ_CMN_PLL=m CONFIG_IPQ_GCC_5018=y CONFIG_IPQ_GCC_5332=y CONFIG_IPQ_GCC_6018=y
The common PLL clock controller provides fixed rate output clocks to the hardware blocks that enable ethernet function on IPQ platform. Signed-off-by: Luo Jie <quic_luoj@quicinc.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+)