diff mbox series

[4/4] arm64: dts: qcom: Add common PLL node for IPQ9574 SoC

Message ID 20240808-qcom_ipq_cmnpll-v1-4-b0631dcbf785@quicinc.com (mailing list archive)
State New, archived
Headers show
Series Add common PLL clock controller driver for IPQ9574 | expand

Commit Message

Luo Jie Aug. 8, 2024, 2:03 p.m. UTC 
The common PLL clock controller allows selection of an input
clock rate from a defined set of input clock rates. It in-turn
supplies fixed rate output clocks to the hardware blocks that
provide ethernet functions, such as PPE (Packet Process Engine)
and connected switch or PHY.

Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi |  6 +++++-
 arch/arm64/boot/dts/qcom/ipq9574.dtsi            | 22 +++++++++++++++++++++-
 2 files changed, 26 insertions(+), 2 deletions(-)

Comments

Krzysztof Kozlowski Aug. 8, 2024, 2:45 p.m. UTC | #1 
On 08/08/2024 16:03, Luo Jie wrote:

>  
>  /dts-v1/;
> @@ -167,3 +167,7 @@ &usb3 {
>  &xo_board_clk {
>  	clock-frequency = <24000000>;
>  };
> +
> +&cmn_pll_ref_clk {

Please follow DTS coding style.

> +	clock-frequency = <48000000>;
> +};



Best regards,
Krzysztof
Luo Jie Aug. 9, 2024, 11:23 a.m. UTC | #2 
On 8/8/2024 10:45 PM, Krzysztof Kozlowski wrote:
> On 08/08/2024 16:03, Luo Jie wrote:
> 
>>   
>>   /dts-v1/;
>> @@ -167,3 +167,7 @@ &usb3 {
>>   &xo_board_clk {
>>   	clock-frequency = <24000000>;
>>   };
>> +
>> +&cmn_pll_ref_clk {
> 
> Please follow DTS coding style.

Ok. Thanks for pointing to this. I will move &cmn_pll_ref_clk before
&xo_board_clk to make the DTS ordering alpha-numerical by the node name.

> 
>> +	clock-frequency = <48000000>;
>> +};
> 
> 
> 
> Best regards,
> Krzysztof
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
index 91e104b0f865..26bc2de7f99a 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
@@ -3,7 +3,7 @@ 
  * IPQ9574 RDP board common device tree source
  *
  * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 /dts-v1/;
@@ -167,3 +167,7 @@  &usb3 {
 &xo_board_clk {
 	clock-frequency = <24000000>;
 };
+
+&cmn_pll_ref_clk {
+	clock-frequency = <48000000>;
+};
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 48dfafea46a7..ad7789dc686e 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -3,7 +3,7 @@ 
  * IPQ9574 SoC device tree source
  *
  * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <dt-bindings/clock/qcom,apss-ipq.h>
@@ -28,6 +28,11 @@  xo_board_clk: xo-board-clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 		};
+
+		cmn_pll_ref_clk: cmn-pll-ref-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+	       };
 	};
 
 	cpus {
@@ -226,6 +231,21 @@  rpm_msg_ram: sram@60000 {
 			reg = <0x00060000 0x6000>;
 		};
 
+		clock-controller@9b000 {
+			compatible = "qcom,ipq9574-cmn-pll";
+			reg = <0x0009b000 0x800>;
+			clocks = <&cmn_pll_ref_clk>,
+				 <&gcc GCC_CMN_12GPLL_AHB_CLK>,
+				 <&gcc GCC_CMN_12GPLL_SYS_CLK>;
+			clock-names = "ref", "ahb", "sys";
+			clock-output-names = "ppe-353mhz",
+					     "eth0-50mhz",
+					     "eth1-50mhz",
+					     "eth2-50mhz",
+					     "eth-25mhz";
+			#clock-cells = <1>;
+		};
+
 		rng: rng@e3000 {
 			compatible = "qcom,prng-ee";
 			reg = <0x000e3000 0x1000>;