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Thu, 8 Aug 2024 14:04:18 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 8 Aug 2024 07:04:13 -0700 From: Luo Jie Date: Thu, 8 Aug 2024 22:03:15 +0800 Subject: [PATCH 4/4] arm64: dts: qcom: Add common PLL node for IPQ9574 SoC MIME-Version: 1.0 Message-ID: <20240808-qcom_ipq_cmnpll-v1-4-b0631dcbf785@quicinc.com> References: <20240808-qcom_ipq_cmnpll-v1-0-b0631dcbf785@quicinc.com> In-Reply-To: <20240808-qcom_ipq_cmnpll-v1-0-b0631dcbf785@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio CC: , , , , , , , , , , Luo Jie X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1723125835; l=2716; i=quic_luoj@quicinc.com; s=20240808; h=from:subject:message-id; bh=6oUq/Dzs0hO7kZwOks3HUIxjCjlf6sj6hTn2ghPIYtI=; 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It in-turn supplies fixed rate output clocks to the hardware blocks that provide ethernet functions, such as PPE (Packet Process Engine) and connected switch or PHY. Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 6 +++++- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 22 +++++++++++++++++++++- 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi index 91e104b0f865..26bc2de7f99a 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi @@ -3,7 +3,7 @@ * IPQ9574 RDP board common device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -167,3 +167,7 @@ &usb3 { &xo_board_clk { clock-frequency = <24000000>; }; + +&cmn_pll_ref_clk { + clock-frequency = <48000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 48dfafea46a7..ad7789dc686e 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -3,7 +3,7 @@ * IPQ9574 SoC device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -28,6 +28,11 @@ xo_board_clk: xo-board-clk { compatible = "fixed-clock"; #clock-cells = <0>; }; + + cmn_pll_ref_clk: cmn-pll-ref-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; }; cpus { @@ -226,6 +231,21 @@ rpm_msg_ram: sram@60000 { reg = <0x00060000 0x6000>; }; + clock-controller@9b000 { + compatible = "qcom,ipq9574-cmn-pll"; + reg = <0x0009b000 0x800>; + clocks = <&cmn_pll_ref_clk>, + <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>; + clock-names = "ref", "ahb", "sys"; + clock-output-names = "ppe-353mhz", + "eth0-50mhz", + "eth1-50mhz", + "eth2-50mhz", + "eth-25mhz"; + #clock-cells = <1>; + }; + rng: rng@e3000 { compatible = "qcom,prng-ee"; reg = <0x000e3000 0x1000>;