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AJvYcCUZw8VBmeImZGg58Y6sN1ToqKm49jTOjzsSaq6L23hA/XGw4sgR3BRY+4eNJtpAm9AR4GyTSVeDFSslBYU0hmYs4R3U2SQCBHd/6X3lwnyFiezkUXJ962q3vblk7N9MU5ss80DpSjFgqDvinA+dYkNn6ii0LT56Ii8= X-Gm-Message-State: AOJu0YwxRc2jSC9+eHzp7PI5dEee5hUfrXBmzlfMy3sPGDP8N/JD1n0m Xg295FRr5+UhaiPnKBOcu4KJetL7smWmE5EgMjkUIu+k8AXbI13b X-Google-Smtp-Source: AGHT+IFqgjG/ZrWb/Pbr+iWfuP6MYtfTQEA9uAjaJ7m+O7kUCxqIuJ0GXMYR7yQXBdrAQ/yTcfLGTA== X-Received: by 2002:a17:902:ce8f:b0:1fb:a38b:c5a0 with SMTP id d9443c01a7336-200ae597aa7mr6144245ad.31.1723189000278; Fri, 09 Aug 2024 00:36:40 -0700 (PDT) Received: from localhost.localdomain ([113.30.217.222]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ff58f5b349sm136588855ad.108.2024.08.09.00.36.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Aug 2024 00:36:39 -0700 (PDT) From: Anand Moon To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Heiko Stuebner Cc: Anand Moon , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2] PCI: dw-rockchip: Enable async probe by default Date: Fri, 9 Aug 2024 13:06:09 +0530 Message-ID: <20240809073610.2517-1-linux.amoon@gmail.com> X-Mailer: git-send-email 2.44.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240809_003641_817269_22D6991B X-CRM114-Status: GOOD ( 14.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Rockchip DWC PCIe driver currently waits for the combo PHY link (PCIe 3.0, PCIe 2.0, and SATA 3.0) to be established link training during boot, it also waits for the link to be up, which could consume several milliseconds during boot. To optimize boot time, this commit allows asynchronous probing. This change enables the PCIe link establishment to occur in the background while other devices are being probed. Signed-off-by: Anand Moon --- v2: update the commit message to describe the changs. --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 1 + 1 file changed, 1 insertion(+) base-commit: ee9a43b7cfe2d8a3520335fea7d8ce71b8cabd9d diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 1170e1107508..7a895b66e4e4 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -616,6 +616,7 @@ static struct platform_driver rockchip_pcie_driver = { .name = "rockchip-dw-pcie", .of_match_table = rockchip_pcie_of_match, .suppress_bind_attrs = true, + .probe_type = PROBE_PREFER_ASYNCHRONOUS, }, .probe = rockchip_pcie_probe, };