| Message ID | 20240810214621.14417-2-florian.fainelli@broadcom.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Support for I/O width within ARM SCMI SHMEM | expand |
Le 10/08/2024 à 23:46, Florian Fainelli a écrit : > Some SRAMs need to be accessed with a specific access width, define > the 'reg-io-width' property specifying such access sizes. > > Signed-off-by: Florian Fainelli <florian.fainelli-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> > --- > Documentation/devicetree/bindings/sram/sram.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml > index 0922d1f71ba8..18e42fb36846 100644 > --- a/Documentation/devicetree/bindings/sram/sram.yaml > +++ b/Documentation/devicetree/bindings/sram/sram.yaml > @@ -101,6 +101,12 @@ patternProperties: > IO mem address range, relative to the SRAM range. > maxItems: 1 > > + reg-io-width: > + description: > + The size (in bytse) of the IO accesses that should be performed on the Typo: in bytes > + SRAM. > + enum: [1, 2, 4, 8] > + > pool: > description: > Indicates that the particular reserved SRAM area is addressable
On 10/08/2024 23:46, Florian Fainelli wrote: > Some SRAMs need to be accessed with a specific access width, define > the 'reg-io-width' property specifying such access sizes. > > Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com> > --- > Documentation/devicetree/bindings/sram/sram.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On Sat, Aug 10, 2024 at 02:46:20PM -0700, Florian Fainelli wrote: > Some SRAMs need to be accessed with a specific access width, define > the 'reg-io-width' property specifying such access sizes. IMO, those SRAMs should have a specific compatible. That restriction makes them less usable. OTOH, it is a standard property. Shrug. > > Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com> > --- > Documentation/devicetree/bindings/sram/sram.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml > index 0922d1f71ba8..18e42fb36846 100644 > --- a/Documentation/devicetree/bindings/sram/sram.yaml > +++ b/Documentation/devicetree/bindings/sram/sram.yaml > @@ -101,6 +101,12 @@ patternProperties: > IO mem address range, relative to the SRAM range. > maxItems: 1 > > + reg-io-width: > + description: > + The size (in bytse) of the IO accesses that should be performed on the > + SRAM. > + enum: [1, 2, 4, 8] > + > pool: > description: > Indicates that the particular reserved SRAM area is addressable > -- > 2.25.1 >
diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml index 0922d1f71ba8..18e42fb36846 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -101,6 +101,12 @@ patternProperties: IO mem address range, relative to the SRAM range. maxItems: 1 + reg-io-width: + description: + The size (in bytse) of the IO accesses that should be performed on the + SRAM. + enum: [1, 2, 4, 8] + pool: description: Indicates that the particular reserved SRAM area is addressable
Some SRAMs need to be accessed with a specific access width, define the 'reg-io-width' property specifying such access sizes. Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com> --- Documentation/devicetree/bindings/sram/sram.yaml | 6 ++++++ 1 file changed, 6 insertions(+)