@@ -7,6 +7,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/st,stm32mp25-rcc.h>
#include <dt-bindings/regulator/st,stm32mp25-regulator.h>
+#include <dt-bindings/phy/phy.h>
/ {
#address-cells = <2>;
@@ -518,6 +519,22 @@ i2c8: i2c@46040000 {
status = "disabled";
};
+ combophy: phy@480c0000 {
+ compatible = "st,stm32mp25-combophy";
+ reg = <0x480c0000 0x1000>;
+ #phy-cells = <1>;
+ clocks = <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>;
+ clock-names = "apb-clk", "ker-clk";
+ resets = <&rcc USB3PCIEPHY_R>;
+ reset-names = "phy-rst";
+ st,syscfg = <&syscfg>;
+ access-controllers = <&rifsc 67>;
+ power-domains = <&CLUSTER_PD>;
+ wakeup-source;
+ interrupts-extended = <&exti1 45 IRQ_TYPE_EDGE_FALLING>;
+ status = "disabled";
+ };
+
sdmmc1: mmc@48220000 {
compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00353180>;
Add support for COMBOPHY which is used either by the USB3 and PCIe controller. USB3 or PCIe mode is done with phy_set_mode(). PCIe internal reference clock can be generated from the internal clock source or optionnaly from an external 100Mhz pad. Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)