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[v3,16/18] KVM: arm64: nv: Make AT+PAN instructions aware of FEAT_PAN3

Message ID 20240813100540.1955263-17-maz@kernel.org (mailing list archive)
State New, archived
Headers show
Series KVM: arm64: nv: Add support for address translation instructions | expand

Commit Message

Marc Zyngier Aug. 13, 2024, 10:05 a.m. UTC
FEAT_PAN3 added a check for executable permissions to FEAT_PAN2.
Add the required SCTLR_ELx.EPAN and descriptor checks to handle
this correctly.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/kvm/at.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

Comments

Alexandru Elisei Aug. 15, 2024, 4:47 p.m. UTC | #1
Hi Marc,

On Tue, Aug 13, 2024 at 11:05:38AM +0100, Marc Zyngier wrote:
> FEAT_PAN3 added a check for executable permissions to FEAT_PAN2.
> Add the required SCTLR_ELx.EPAN and descriptor checks to handle
> this correctly.
> 
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
>  arch/arm64/kvm/at.c | 17 ++++++++++++++++-
>  1 file changed, 16 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/kvm/at.c b/arch/arm64/kvm/at.c
> index 6d5555e98557..c134bcd0338d 100644
> --- a/arch/arm64/kvm/at.c
> +++ b/arch/arm64/kvm/at.c
> @@ -728,6 +728,21 @@ static u64 compute_par_s1(struct kvm_vcpu *vcpu, struct s1_walk_result *wr,
>  	return par;
>  }
>  
> +static bool pan3_enabled(struct kvm_vcpu *vcpu, enum trans_regime regime)
> +{
> +	u64 sctlr;
> +
> +	if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR1_EL1, PAN, PAN3))
> +		return false;
> +
> +	if (regime == TR_EL10)
> +		sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1);
> +	else
> +		sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL2);
> +
> +	return sctlr & SCTLR_EL1_EPAN;

Checked that the EPAN is on the same position for SCTLR_EL1 and SCTLR_EL2.

> +}
> +
>  static u64 handle_at_slow(struct kvm_vcpu *vcpu, u32 op, u64 vaddr)
>  {
>  	bool perm_fail, ur, uw, ux, pr, pw, px;
> @@ -794,7 +809,7 @@ static u64 handle_at_slow(struct kvm_vcpu *vcpu, u32 op, u64 vaddr)
>  			bool pan;
>  
>  			pan = *vcpu_cpsr(vcpu) & PSR_PAN_BIT;
> -			pan &= ur || uw;
> +			pan &= ur || uw || (pan3_enabled(vcpu, wi.regime) && ux);
>  			pw &= !pan;
>  			pr &= !pan;
>  		}

Matches AArch64.S1DirectBasePermissions().

Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>

Thanks,
Alex
diff mbox series

Patch

diff --git a/arch/arm64/kvm/at.c b/arch/arm64/kvm/at.c
index 6d5555e98557..c134bcd0338d 100644
--- a/arch/arm64/kvm/at.c
+++ b/arch/arm64/kvm/at.c
@@ -728,6 +728,21 @@  static u64 compute_par_s1(struct kvm_vcpu *vcpu, struct s1_walk_result *wr,
 	return par;
 }
 
+static bool pan3_enabled(struct kvm_vcpu *vcpu, enum trans_regime regime)
+{
+	u64 sctlr;
+
+	if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR1_EL1, PAN, PAN3))
+		return false;
+
+	if (regime == TR_EL10)
+		sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1);
+	else
+		sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL2);
+
+	return sctlr & SCTLR_EL1_EPAN;
+}
+
 static u64 handle_at_slow(struct kvm_vcpu *vcpu, u32 op, u64 vaddr)
 {
 	bool perm_fail, ur, uw, ux, pr, pw, px;
@@ -794,7 +809,7 @@  static u64 handle_at_slow(struct kvm_vcpu *vcpu, u32 op, u64 vaddr)
 			bool pan;
 
 			pan = *vcpu_cpsr(vcpu) & PSR_PAN_BIT;
-			pan &= ur || uw;
+			pan &= ur || uw || (pan3_enabled(vcpu, wi.regime) && ux);
 			pw &= !pan;
 			pr &= !pan;
 		}