From patchwork Thu Aug 15 15:59:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 13764999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E50E0C52D7C for ; Thu, 15 Aug 2024 17:16:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-Transfer-Encoding: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=/hrWt2518Dz3e6W8kH7P0VKhIxnD9cKs1yguoTtW/UY=; b=eqiFxNQ0uTMV2jrikt1PTyDvbW aIdDgTezvbri7bfZwBWfCDt+PJ0M4IRPTosHbSuj9FjyHKna1jKzm0pJbWkX6B1Eqp2kjTIcFQOWU GmXa3+UO+SO6N4GlcYFUsAGWmy3EeTTfHZ0vfX/Tx+tTW05iYs3uL+DtOmEBhOzTDkuCmXeS+LFz6 MJOnR9qZwcX5+8h5ORjgn9DQ8kviQnZn0hRQlehiAmRSNrpXZ32XvRiqL6Ur3TJ1vg0bI4t757C5s ZRPyYZJX+yh2RFryONfS3u5VixUTU4g6HStmU/tkiKyOSBEkhPIRhCQRhSSGjifaG4YzBvFMjC0tX xvjhJchQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1see4w-0000000Ac3M-3P8y; Thu, 15 Aug 2024 17:16:02 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1secu1-0000000AS84-2qcu for linux-arm-kernel@bombadil.infradead.org; Thu, 15 Aug 2024 16:00:41 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Type:MIME-Version:Message-ID: Date:Subject:CC:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:In-Reply-To:References; bh=/hrWt2518Dz3e6W8kH7P0VKhIxnD9cKs1yguoTtW/UY=; b=H/1XFrHx+aaBS5divJOSjA9Odw P3JeNPabk9rV2dxCACXsXAcS6kmBY5gNiundel9LFdq5RFtSp4rX+C+W190JXvfxt4at2JZe5DisV SNEybzJv6HS1XsLe+fs0zVuRWmUJCvKFQn6AugP+uhM1ugqMZ2saPrwjf48j74vxhKtUs1SMebbJ4 eNRY7FkB80iplj07rRStp0OaXBLcC30V0vOGgOQMfMoGGylQqkZjMsp2mwTxavVjBWsbB4FDyMpmq GQyJYSgSddLS0ixWv1ldfwfOL79khGZtqJDZIqUsbB3tWWZc88rzkUXyIniWZadZKyHEMwRUMsVcT pSRAajdw==; Received: from frasgout.his.huawei.com ([185.176.79.56]) by desiato.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1secty-00000008Qws-1b5Z for linux-arm-kernel@lists.infradead.org; Thu, 15 Aug 2024 16:00:40 +0000 Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4Wl8rz19LXz6D92H; Thu, 15 Aug 2024 23:57:23 +0800 (CST) Received: from lhrpeml500005.china.huawei.com (unknown [7.191.163.240]) by mail.maildlp.com (Postfix) with ESMTPS id E43AD140119; Fri, 16 Aug 2024 00:00:19 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by lhrpeml500005.china.huawei.com (7.191.163.240) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Thu, 15 Aug 2024 17:00:14 +0100 From: Shameer Kolothum To: , CC: , , , , , , , , Subject: [PATCH v2] KVM: arm64: Make the exposed feature bits in AA64DFR0_EL1 writable from userspace Date: Thu, 15 Aug 2024 16:59:54 +0100 Message-ID: <20240815155954.85480-1-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To lhrpeml500005.china.huawei.com (7.191.163.240) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240815_170038_542646_5932446C X-CRM114-Status: GOOD ( 14.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org KVM exposes the OS double lock feature bit to Guests but returns RAZ/WI on Guest OSDLR_EL1 access. This breaks Guest migration between systems where this feature differ. Add support to make this feature writable from userspace by setting the mask bit. While at it, set the mask bits for the exposed WRPs(Number of Watchpoints) as well. Also update the selftest to cover these fields. However we still can't make BRPs and CTX_CMPs fields writable, because as per ARM ARM DDI 0487K.a, section G2.8.2 Breakpoint types and linking of breakpoints, highest numbered breakpoints must be context aware breakpoints. And it will be problematic if userspace decreases the number of non-context aware breakpoints as it will make the context aware breakpoints for the guest mapped to a wrong one. Signed-off-by: Shameer Kolothum Reviewed-by: Oliver Upton --- v1 --> v2: Removed making BRPs and CTX_CMPs writable. v1: https://lore.kernel.org/all/20240813142835.77180-1-shameerali.kolothum.thodi@huawei.com/ --- arch/arm64/kvm/sys_regs.c | 13 ++++++++++++- tools/testing/selftests/kvm/aarch64/set_id_regs.c | 2 ++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c90324060436..e77cd6d1abb5 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2376,7 +2376,18 @@ static const struct sys_reg_desc sys_reg_descs[] = { .get_user = get_id_reg, .set_user = set_id_aa64dfr0_el1, .reset = read_sanitised_id_aa64dfr0_el1, - .val = ID_AA64DFR0_EL1_PMUVer_MASK | + /* + * We can't still make BRPs and CTX_CMPx writable as highest + * numbered breakpoints must be context aware breakpoints(ARM ARM + * DDI 0487K.a, section G2.8.2 Breakpoint types and linking of + * breakpoints). Hence, if the number of non-context aware breakpoints + * for the Guest is decreased by userspace, that will be problematic + * as KVM will map context aware breakpoints for the vCPU to different + * numbered breakpoints for the pCPU. + */ + .val = ID_AA64DFR0_EL1_DoubleLock_MASK | + ID_AA64DFR0_EL1_WRPs_MASK | + ID_AA64DFR0_EL1_PMUVer_MASK | ID_AA64DFR0_EL1_DebugVer_MASK, }, ID_SANITISED(ID_AA64DFR1_EL1), ID_UNALLOCATED(5,2), diff --git a/tools/testing/selftests/kvm/aarch64/set_id_regs.c b/tools/testing/selftests/kvm/aarch64/set_id_regs.c index d20981663831..6edc5412abe8 100644 --- a/tools/testing/selftests/kvm/aarch64/set_id_regs.c +++ b/tools/testing/selftests/kvm/aarch64/set_id_regs.c @@ -68,6 +68,8 @@ struct test_feature_reg { } static const struct reg_ftr_bits ftr_id_aa64dfr0_el1[] = { + S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DoubleLock, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, WRPs, 0), S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, PMUVer, 0), REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DebugVer, ID_AA64DFR0_EL1_DebugVer_IMP), REG_FTR_END,