| Message ID | 20240816174259.2056829-7-quic_bibekkum@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs | expand |
Hi Bibek,
kernel test robot noticed the following build warnings:
[auto build test WARNING on joro-iommu/next]
[also build test WARNING on linus/master v6.11-rc4 next-20240822]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Bibek-Kumar-Patro/iommu-arm-smmu-re-enable-context-caching-in-smmu-reset-operation/20240817-014609
base: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git next
patch link: https://lore.kernel.org/r/20240816174259.2056829-7-quic_bibekkum%40quicinc.com
patch subject: [PATCH v14 6/6] iommu/arm-smmu: add support for PRR bit setup
config: arm-randconfig-r071-20240823 (https://download.01.org/0day-ci/archive/20240823/202408230612.1DU9cuSx-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 14.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240823/202408230612.1DU9cuSx-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202408230612.1DU9cuSx-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from include/linux/scatterlist.h:9,
from include/linux/iommu.h:10,
from include/linux/io-pgtable.h:6,
from include/linux/adreno-smmu-priv.h:9,
from drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c:7:
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c: In function 'qcom_adreno_smmu_set_prr_addr':
>> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c:266:41: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
266 | (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_LADDR);
| ^
arch/arm/include/asm/io.h:282:75: note: in definition of macro 'writel_relaxed'
282 | #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
| ^
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c:269:41: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
269 | (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_UADDR);
| ^
arch/arm/include/asm/io.h:282:75: note: in definition of macro 'writel_relaxed'
282 | #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
| ^
vim +266 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
256
257 static void qcom_adreno_smmu_set_prr_addr(const void *cookie, phys_addr_t page_addr)
258 {
259 struct arm_smmu_domain *smmu_domain = (void *)cookie;
260 struct arm_smmu_device *smmu = smmu_domain->smmu;
261 const struct device_node *np = smmu->dev->of_node;
262
263 if (of_device_is_compatible(np, "qcom,smmu-500") &&
264 of_device_is_compatible(np, "qcom,adreno-smmu")) {
265 writel_relaxed(lower_32_bits(page_addr),
> 266 (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_LADDR);
267
268 writel_relaxed(upper_32_bits(page_addr),
269 (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_UADDR);
270 }
271 }
272
On 8/23/2024 4:07 AM, kernel test robot wrote: >>> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c:266:41: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] > 266 | (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_LADDR); > | ^ > arch/arm/include/asm/io.h:282:75: note: in definition of macro 'writel_relaxed' > 282 | #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c) > | ^ > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c:269:41: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] > 269 | (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_UADDR); > | ^ > arch/arm/include/asm/io.h:282:75: note: in definition of macro 'writel_relaxed' > 282 | #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c) This is fixed already in v13, but got missed in v14. I'll take care of this in the next version. regards, Bibek
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index a776c7906c76..f62e20d472d3 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -30,6 +30,7 @@ #define PREFETCH_SHALLOW (1 << PREFETCH_SHIFT) #define PREFETCH_MODERATE (2 << PREFETCH_SHIFT) #define PREFETCH_DEEP (3 << PREFETCH_SHIFT) +#define GFX_ACTLR_PRR (1 << 5) static const struct actlr_config sc7280_apps_actlr_cfg[] = { { 0x0800, 0x04e0, PREFETCH_DEFAULT | CMTLB }, @@ -237,6 +238,40 @@ static void qcom_adreno_smmu_resume_translation(const void *cookie, bool termina arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg); } +static void qcom_adreno_smmu_set_prr_bit(const void *cookie, bool set) +{ + struct arm_smmu_domain *smmu_domain = (void *)cookie; + struct arm_smmu_device *smmu = smmu_domain->smmu; + const struct device_node *np = smmu->dev->of_node; + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; + u32 reg = 0; + + if (of_device_is_compatible(np, "qcom,smmu-500") && + of_device_is_compatible(np, "qcom,adreno-smmu")) { + reg = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR); + reg &= ~GFX_ACTLR_PRR; + if (set) + reg |= FIELD_PREP(GFX_ACTLR_PRR, 1); + arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_ACTLR, reg); + } +} + +static void qcom_adreno_smmu_set_prr_addr(const void *cookie, phys_addr_t page_addr) +{ + struct arm_smmu_domain *smmu_domain = (void *)cookie; + struct arm_smmu_device *smmu = smmu_domain->smmu; + const struct device_node *np = smmu->dev->of_node; + + if (of_device_is_compatible(np, "qcom,smmu-500") && + of_device_is_compatible(np, "qcom,adreno-smmu")) { + writel_relaxed(lower_32_bits(page_addr), + (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_LADDR); + + writel_relaxed(upper_32_bits(page_addr), + (void *)smmu->ioaddr + ARM_SMMU_GFX_PRR_CFG_UADDR); + } +} + #define QCOM_ADRENO_SMMU_GPU_SID 0 static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) @@ -410,6 +445,8 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, priv->get_fault_info = qcom_adreno_smmu_get_fault_info; priv->set_stall = qcom_adreno_smmu_set_stall; priv->resume_translation = qcom_adreno_smmu_resume_translation; + priv->set_prr_bit = qcom_adreno_smmu_set_prr_bit; + priv->set_prr_addr = qcom_adreno_smmu_set_prr_addr; actlrvar = qsmmu->data->actlrvar; if (!actlrvar) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index 172f1b56b879..b3f5ff1ebb8d 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -154,6 +154,8 @@ enum arm_smmu_cbar_type { #define ARM_SMMU_SCTLR_M BIT(0) #define ARM_SMMU_CB_ACTLR 0x4 +#define ARM_SMMU_GFX_PRR_CFG_LADDR 0x6008 +#define ARM_SMMU_GFX_PRR_CFG_UADDR 0x600C #define ARM_SMMU_CB_RESUME 0x8 #define ARM_SMMU_RESUME_TERMINATE BIT(0) diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h index c637e0997f6d..03466eb16933 100644 --- a/include/linux/adreno-smmu-priv.h +++ b/include/linux/adreno-smmu-priv.h @@ -49,7 +49,13 @@ struct adreno_smmu_fault_info { * before set_ttbr0_cfg(). If stalling on fault is enabled, * the GPU driver must call resume_translation() * @resume_translation: Resume translation after a fault - * + * @set_prr_bit: Extendible interface to be used by GPU to modify the + * ACTLR register bits, currently used to configure + * Partially-Resident-Region (PRR) bit for feature's + * setup and reset sequence as requested. + * @set_prr_addr: Configure the PRR_CFG_*ADDR register with the + * physical address of PRR page passed from + * GPU driver. * * The GPU driver (drm/msm) and adreno-smmu work together for controlling * the GPU's SMMU instance. This is by necessity, as the GPU is directly @@ -67,6 +73,8 @@ struct adreno_smmu_priv { void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info); void (*set_stall)(const void *cookie, bool enabled); void (*resume_translation)(const void *cookie, bool terminate); + void (*set_prr_bit)(const void *cookie, bool set); + void (*set_prr_addr)(const void *cookie, phys_addr_t page_addr); }; #endif /* __ADRENO_SMMU_PRIV_H */
Add an adreno-smmu-priv interface for drm/msm to call into arm-smmu-qcom and initiate the PRR bit setup or reset sequence as per request. This will be used by GPU to setup the PRR bit and related configuration registers through adreno-smmu private interface instead of directly poking the smmu hardware. Suggested-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com> --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 37 ++++++++++++++++++++++ drivers/iommu/arm/arm-smmu/arm-smmu.h | 2 ++ include/linux/adreno-smmu-priv.h | 10 +++++- 3 files changed, 48 insertions(+), 1 deletion(-) -- 2.34.1