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AJvYcCWz7MGloOPIsm/Si+X6aNY4kkgiMLofHjcVAoyE62fj2y70DMYm4fvzaunmS64ton6AnIHcqBv3izbEsJR6SYM4mqM/uh99s2whD270Bk6iju+cI4o= X-Gm-Message-State: AOJu0Ywu4my4TnFi/VavAerJQN6HaffqZL2ViSYswICrCEe2gQX9Vaky ZlJOuN/Wt5mBm8/lfQxCq0AZypoFK68A2N7ghj76Q8TH+aTKw+4L X-Google-Smtp-Source: AGHT+IEhrh56okZbmvy9C8HwDNy5xwpiZQq52uQq/hi8jnlhVoMry9g9W6uYptcJ6SG8XC/2yTyWnQ== X-Received: by 2002:a17:907:7d8b:b0:a77:c051:36a9 with SMTP id a640c23a62f3a-a8394dc741bmr339367066b.9.1723830850657; Fri, 16 Aug 2024 10:54:10 -0700 (PDT) Received: from localhost.localdomain ([2a02:ab88:3711:c80:e7a7:e025:f1a5:ef78]) by smtp.googlemail.com with ESMTPSA id a640c23a62f3a-a83838c66b6sm290520866b.16.2024.08.16.10.54.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Aug 2024 10:54:10 -0700 (PDT) From: David Virag To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd Cc: David Virag , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/2] clk: samsung: clk-pll: Add support for pll_1418x Date: Fri, 16 Aug 2024 19:50:31 +0200 Message-ID: <20240816175034.769628-2-virag.david003@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240816175034.769628-1-virag.david003@gmail.com> References: <20240816175034.769628-1-virag.david003@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240816_105412_853382_747FC134 X-CRM114-Status: GOOD ( 19.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org pll1418x is used in Exynos7885 SoC for USB PHY clock. Operation-wise it is very similar to pll0822x, except that MDIV is only 9 bits wide instead of 10, and we use the CON1 register in the PLL macro's "con" parameter instead of CON3 like this: PLL(pll_1418x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk", PLL_LOCKTIME_PLL_USB, PLL_CON0_PLL_USB, pll_usb_rate_table), Technically the PLL should work fine with pll0822x code if the PLL tables are correct, but it's more "correct" to actually update the mask. Signed-off-by: David Virag --- Changes in v2: - None Changes in v3: - Simplify set_rate part drivers/clk/samsung/clk-pll.c | 18 +++++++++++++++--- drivers/clk/samsung/clk-pll.h | 1 + 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 4be879ab917e..4307cd534ee6 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -430,6 +430,9 @@ static const struct clk_ops samsung_pll36xx_clk_min_ops = { #define PLL0822X_LOCK_STAT_SHIFT (29) #define PLL0822X_ENABLE_SHIFT (31) +/* PLL1418x is similar to PLL0822x, except that MDIV is one bit smaller */ +#define PLL1418X_MDIV_MASK (0x1FF) + static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -438,7 +441,10 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw, u64 fvco = parent_rate; pll_con3 = readl_relaxed(pll->con_reg); - mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK; + if (pll->type != pll_1418x) + mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK; + else + mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL1418X_MDIV_MASK; pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK; sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK; @@ -456,7 +462,12 @@ static int samsung_pll0822x_set_rate(struct clk_hw *hw, unsigned long drate, { const struct samsung_pll_rate_table *rate; struct samsung_clk_pll *pll = to_clk_pll(hw); - u32 pll_con3; + u32 mdiv_mask, pll_con3; + + if (pll->type != pll_1418x) + mdiv_mask = PLL0822X_MDIV_MASK; + else + mdiv_mask = PLL1418X_MDIV_MASK; /* Get required rate settings from table */ rate = samsung_get_pll_settings(pll, drate); @@ -468,7 +479,7 @@ static int samsung_pll0822x_set_rate(struct clk_hw *hw, unsigned long drate, /* Change PLL PMS values */ pll_con3 = readl_relaxed(pll->con_reg); - pll_con3 &= ~((PLL0822X_MDIV_MASK << PLL0822X_MDIV_SHIFT) | + pll_con3 &= ~((mdiv_mask << PLL0822X_MDIV_SHIFT) | (PLL0822X_PDIV_MASK << PLL0822X_PDIV_SHIFT) | (PLL0822X_SDIV_MASK << PLL0822X_SDIV_SHIFT)); pll_con3 |= (rate->mdiv << PLL0822X_MDIV_SHIFT) | @@ -1317,6 +1328,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, init.ops = &samsung_pll35xx_clk_ops; break; case pll_1417x: + case pll_1418x: case pll_0818x: case pll_0822x: case pll_0516x: diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index ffd3d52c0dec..1efbe4c446d0 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -30,6 +30,7 @@ enum samsung_pll_type { pll_2650x, pll_2650xx, pll_1417x, + pll_1418x, pll_1450x, pll_1451x, pll_1452x,