Message ID | 20240820-c3_add_node-v2-1-8fd3f06b7bce@amlogic.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | add some node for amlogic c3 | expand |
On Tue, Aug 20, 2024 at 05:41:56PM +0800, Xianwei Zhao wrote: > Add C3 PLL controller input clock parameters "fix". > > The clock named "fix" was initially implemented in PLL clock controller driver. > However, some registers required secure zone access, so we moved it to > the secure zone (BL31) and accessed it through SCMI. Since the PLL clock > driver needs to use this clock, the "fix" clock is used as an input source. > We updated the driver but forgot to modify the binding accordingly, > so we are adding it here. > > It is an ABI break but on a new and immature platform. > Noboby could really use that platform at this stage, so nothing is going > to break on anyone really. > > Fixes: 0e6be855a96d ("dt-bindings: clock: add Amlogic C3 PLL clock controller") > Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml index 43de3c6fc1cf..700865cc9792 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml +++ b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml @@ -24,11 +24,13 @@ properties: items: - description: input top pll - description: input mclk pll + - description: input fix pll clock-names: items: - const: top - const: mclk + - const: fix "#clock-cells": const: 1 @@ -52,8 +54,9 @@ examples: compatible = "amlogic,c3-pll-clkc"; reg = <0x0 0x8000 0x0 0x1a4>; clocks = <&scmi_clk 2>, - <&scmi_clk 5>; - clock-names = "top", "mclk"; + <&scmi_clk 5>, + <&scmi_clk 12>; + clock-names = "top", "mclk", "fix"; #clock-cells = <1>; }; };