| Message ID | 20240820104034.15607-3-hnagalla@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add R5F and C7x DSP nodes for AM62a SoC | expand |
On 8/20/24 5:40 AM, Hari Nagalla wrote: > AM62A SoCs have a single R5F core in the MCU voltage domain. The MCU > domain also has a 512KB sram memory, the R5F core can use for > applications needing fast memory access. > > Signed-off-by: Hari Nagalla <hnagalla@ti.com> > --- > arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi | 35 ++++++++++++++++++++++++ > 1 file changed, 35 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi > index 8c36e56f4138..803da3cce336 100644 > --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi > @@ -6,6 +6,17 @@ > */ > > &cbass_mcu { > + mcu_ram: sram@79100000 { This change doesn't belong to this patch, this memory can be used by other components in the system and is not exclusive to the R5F firmware. Let's add this node later so it can be discussed on its own and not block this otherwise correct series. > + compatible = "mmio-sram"; > + reg = <0x00 0x79100000 0x00 0x80000>; > + ranges = <0x00 0x00 0x79100000 0x80000>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + mcu1-sram@0 { > + reg = <0x0 0x80000>; > + }; > + }; Need newline here if you were going to keep this node.. > mcu_pmx0: pinctrl@4084000 { > compatible = "pinctrl-single"; > reg = <0x00 0x04084000 0x00 0x88>; > @@ -167,4 +178,28 @@ mcu_mcan1: can@4e18000 { > bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; > status = "disabled"; > }; > + > + mcu_r5fss0: r5fss@79000000 { > + compatible = "ti,am62-r5fss"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x79000000 0x00 0x79000000 0x8000>, > + <0x79020000 0x00 0x79020000 0x8000>; > + power-domains = <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>; Newline here. Andrew > + mcu_r5fss0_core0: r5f@79000000 { > + compatible = "ti,am62-r5f"; > + reg = <0x79000000 0x00008000>, > + <0x79020000 0x00008000>; > + reg-names = "atcm", "btcm"; > + ti,sci = <&dmsc>; > + ti,sci-dev-id = <9>; > + ti,sci-proc-ids = <0x03 0xff>; > + resets = <&k3_reset 9 1>; > + firmware-name = "am62a-mcu-r5f0_0-fw"; > + ti,atcm-enable = <0>; > + ti,btcm-enable = <1>; > + ti,loczrama = <0>; > + sram = <&mcu_ram>; > + }; > + }; > };
diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi index 8c36e56f4138..803da3cce336 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -6,6 +6,17 @@ */ &cbass_mcu { + mcu_ram: sram@79100000 { + compatible = "mmio-sram"; + reg = <0x00 0x79100000 0x00 0x80000>; + ranges = <0x00 0x00 0x79100000 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + + mcu1-sram@0 { + reg = <0x0 0x80000>; + }; + }; mcu_pmx0: pinctrl@4084000 { compatible = "pinctrl-single"; reg = <0x00 0x04084000 0x00 0x88>; @@ -167,4 +178,28 @@ mcu_mcan1: can@4e18000 { bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; status = "disabled"; }; + + mcu_r5fss0: r5fss@79000000 { + compatible = "ti,am62-r5fss"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x79000000 0x00 0x79000000 0x8000>, + <0x79020000 0x00 0x79020000 0x8000>; + power-domains = <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>; + mcu_r5fss0_core0: r5f@79000000 { + compatible = "ti,am62-r5f"; + reg = <0x79000000 0x00008000>, + <0x79020000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <9>; + ti,sci-proc-ids = <0x03 0xff>; + resets = <&k3_reset 9 1>; + firmware-name = "am62a-mcu-r5f0_0-fw"; + ti,atcm-enable = <0>; + ti,btcm-enable = <1>; + ti,loczrama = <0>; + sram = <&mcu_ram>; + }; + }; };
AM62A SoCs have a single R5F core in the MCU voltage domain. The MCU domain also has a 512KB sram memory, the R5F core can use for applications needing fast memory access. Signed-off-by: Hari Nagalla <hnagalla@ti.com> --- arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi | 35 ++++++++++++++++++++++++ 1 file changed, 35 insertions(+)