diff mbox series

[v2] arm64: dts: ti: k3-am654-idk: Add Support for MCAN

Message ID 20240821205414.1706661-1-jm@ti.com (mailing list archive)
State New, archived
Headers show
Series [v2] arm64: dts: ti: k3-am654-idk: Add Support for MCAN | expand

Commit Message

Judith Mendez Aug. 21, 2024, 8:54 p.m. UTC 
From: Faiz Abbas <faiz_abbas@ti.com>

There are two MCAN instances present on the am65x SoC [0].
Since there are two CAN transceivers on the IDK application
board for AM654 EVM [1], enable m_can0 and m_can1, add the
two corresponding CAN transceiver nodes, and set a maximum
data rate of 5 Mbps.

[0] https://www.ti.com/lit/ds/symlink/am6548.pdf
[1] https://www.ti.com/lit/zip/sprr382

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Judith Mendez <jm@ti.com>
---
Changes since v1:
- Move status DT property to end of m_can nodes according to
  dts-coding-style

Link to v1:
https://lore.kernel.org/linux-devicetree/20240820193420.29184-1-jm@ti.com/
---
 arch/arm64/boot/dts/ti/k3-am654-idk.dtso | 61 ++++++++++++++++++++++++
 1 file changed, 61 insertions(+)


base-commit: e3cce1229c34b5c28f103361c4d6b3ef17302d5d

Comments

Nishanth Menon Aug. 24, 2024, 7:54 p.m. UTC | #1 
Hi Judith Mendez,

On Wed, 21 Aug 2024 15:54:14 -0500, Judith Mendez wrote:
> There are two MCAN instances present on the am65x SoC [0].
> Since there are two CAN transceivers on the IDK application
> board for AM654 EVM [1], enable m_can0 and m_can1, add the
> two corresponding CAN transceiver nodes, and set a maximum
> data rate of 5 Mbps.
> 
> [0] https://www.ti.com/lit/ds/symlink/am6548.pdf
> [1] https://www.ti.com/lit/zip/sprr382
> 
> [...]

I have applied the following to branch ti-k3-dts-next on [1].
Thank you!

[1/1] arm64: dts: ti: k3-am654-idk: Add Support for MCAN
      commit: f0f961ab9c9652c2f07bd7120a5b2b462ad6fd92

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/ti/k3-am654-idk.dtso b/arch/arm64/boot/dts/ti/k3-am654-idk.dtso
index 8bdb87fcbde00..97f7eb34b99a6 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-idk.dtso
+++ b/arch/arm64/boot/dts/ti/k3-am654-idk.dtso
@@ -8,6 +8,7 @@ 
 /dts-v1/;
 /plugin/;
 
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/net/ti-dp83867.h>
 #include "k3-pinctrl.h"
 
@@ -154,6 +155,24 @@  icssg1_emac1: port@1 {
 			};
 		};
 	};
+
+	transceiver1: can-phy0 {
+		compatible = "ti,tcan1042";
+		#phy-cells = <0>;
+		max-bitrate = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mcan0_gpio_pins_default>;
+		standby-gpios = <&main_gpio1 47 GPIO_ACTIVE_LOW>;
+	};
+
+	transceiver2: can-phy1 {
+		compatible = "ti,tcan1042";
+		#phy-cells = <0>;
+		max-bitrate = <5000000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mcan1_gpio_pins_default>;
+		standby-gpios = <&main_gpio1 67 GPIO_ACTIVE_LOW>;
+	};
 };
 
 &main_pmx0 {
@@ -243,6 +262,34 @@  icssg1_iep0_pins_default: icssg1-iep0-default-pins {
 			AM65X_IOPAD(0x012c, PIN_INPUT, 2) /* (AG26) PRG1_PRU0_GPO19.PRG1_IEP0_EDC_SYNC_OUT0 */
 		>;
 	};
+
+	mcan0_gpio_pins_default: mcan0-gpio-default-pins {
+		pinctrl-single,pins = <
+			AM65X_IOPAD(0x023c, PIN_INPUT, 7) /* (V25) PRG0_PRU0_GPIO18:GPIO1_47 */
+		>;
+	};
+
+	mcan1_gpio_pins_default: mcan1-gpio-default-pins {
+		pinctrl-single,pins = <
+			AM65X_IOPAD(0x028c, PIN_INPUT, 7) /* (Y26) PRG0_PRU1_GPIO18.GPIO1_67 */
+		>;
+	};
+};
+
+&wkup_pmx0 {
+	mcu_mcan0_pins_default: mcu-mcan0-default-pins {
+		pinctrl-single,pins = <
+			AM65X_WKUP_IOPAD(0x00ac, PIN_INPUT_PULLUP, 0) /* (W2) MCU_MCAN0_RX */
+			AM65X_WKUP_IOPAD(0x00a8, PIN_OUTPUT_PULLUP, 0) /* (W1) MCU_MCAN0_TX */
+		>;
+	};
+
+	mcu_mcan1_pins_default: mcu-mcan1-default-pins {
+		pinctrl-single,pins = <
+			AM65X_WKUP_IOPAD(0x00c4, PIN_INPUT_PULLUP, 1) /* (AD3) WKUP_GPIO0_5.MCU_MCAN1_RX */
+			AM65X_WKUP_IOPAD(0x00c0, PIN_OUTPUT_PULLUP, 1) /* (AC3) WKUP_GPIO0_4.MCU_MCAN1_TX */
+		>;
+	};
 };
 
 &icssg0_mdio {
@@ -294,3 +341,17 @@  &icssg1_iep0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&icssg1_iep0_pins_default>;
 };
+
+&m_can0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_mcan0_pins_default>;
+	phys = <&transceiver1>;
+	status = "okay";
+};
+
+&m_can1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_mcan1_pins_default>;
+	phys = <&transceiver2>;
+	status = "okay";
+};