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Mon, 26 Aug 2024 12:22:11 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 26 Aug 2024 12:22:11 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 26 Aug 2024 12:22:11 -0500 Received: from localhost (bb.dhcp.ti.com [128.247.81.12]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47QHMB0i123213; Mon, 26 Aug 2024 12:22:11 -0500 From: Bryan Brattlof Date: Mon, 26 Aug 2024 12:22:10 -0500 Subject: [PATCH v3 4/4] arm64: dts: ti: k3-am62p5-sk: add 1.4ghz opp entry MIME-Version: 1.0 Message-ID: <20240826-opp-v3-4-0934f8309e13@ti.com> References: <20240826-opp-v3-0-0934f8309e13@ti.com> In-Reply-To: <20240826-opp-v3-0-0934f8309e13@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Bryan Brattlof X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1016; i=bb@ti.com; h=from:subject:message-id; bh=bpOlassBoRg3W4gbLK1G5G0YGPD63Zsyvt4g9z263Eo=; b=owNCWmg5MUFZJlNZxCdgMgAAaH///37/vj//3Tf3z1fsdS33z6pvaN/+Odvv149/jB3cwc6wA RtlB2oAekA0BpoNGjR6QGQANNDQBpoDR6gDQANGhkNGj0gaBoND0mINBtCY0xQ5AGg0GQZDQNMI A0yNomJoMmmjIGmjQyBkMhiNGBNAANBow1AMTIaaZGIhkyYgaGgNAaPUYmTEGRkNNGhiBiaYQaY gDIABtCBkGRpiaZA0MIAZBgOHcyiHXlROfJTC5KLGLrAAS4PSIOPLAz0zIdySGdgBNh6UckgAtR 7+gTLmnZcTCu74R9Sy840F6XeALnybi9+ENp5t79cRMsnHrbcy3IcwRum9rN/UB0LKtASJGRwUL UMrRumkyuB0pNNxFXVnMVLNRovrt8dRn4dcR2sCqEg03GQNT6ryYnIaOHkUCSs216AvUBfQqJ2X 3GjPZC3vMWPEUAiHuhQhw2mfBlc4q0apZD07AH76EPDtvqvYjyUfiWKX/Aig04KXR8X1ISHbMU+ dG9p37c48IETmnG7QCXCkdXci4S8OCKce8oTa25JZGbDJCjDDlKudF2zxYQ26+F+/E8me8RgQ+8 tIPDGbg2lfsX6GjVgJnFsTRDAK5abRJTJ0A4OmcglWbGlWDtXWZyhJxXb0F6kLEPiDYBMITJN/b GK/xdyRThQkMQnYDIA= X-Developer-Key: i=bb@ti.com; a=openpgp; fpr=D3D177E40A38DF4D1853FEEF41B90D5D71D56CE0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240826_182225_199388_A5FBFA0A X-CRM114-Status: GOOD ( 10.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The AM62Px reference board is capable of supplying 0v85 to the VDD_CORE which allows the Cortex-A53s to operate at 1.4GHz according to chapter 6.6 of the SoC's data sheet[0] . Append the 1.4Ghz entry to the OPP table to enable this frequency [0] https://www.ti.com/lit/ds/symlink/am62p-q1.pdf Signed-off-by: Bryan Brattlof --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index ff65955551a32..ab5d7a5fc6118 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -128,6 +128,15 @@ led-0 { }; }; + opp-table { + /* Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + tlv320_mclk: clk-0 { #clock-cells = <0>; compatible = "fixed-clock";