From patchwork Tue Aug 27 15:25:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13779703 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9430DC54731 for ; Tue, 27 Aug 2024 15:26:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=KiomNdyd/FOubhGeCy8J78J+5NwNiFGcgqwk/r9M6x0=; b=vYXULlkneQGF7ygR5NDRMd4EFE INZmzs80fBiknzSsQ3W+V5qANCfeM3Bcd6/cGH50eLMzzU12+R0W4bydCHPs2TDuJX0jMIX0NkSFw upTSXdJtaJCz3OghgjLbMeumpU208yltumKugyscfgQNQ+VJ/uf88Vum0P3kT+MszFitaSNIivcVI 4E0x+YSQYWgFecHvVw4wZL5innQ+pkyeeTjKol03f2DilrCXOfA+jvymlqEHubeH2eBUFVhWMA2oJ br7kLGBGefu+myjEZjg4sPBJDSAS1wsqZZlTiSSmJxWTL2JNBSGbnPOxcTVhH2aOdVCaJf2epvgjW oWSeMyaw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1siy5Q-0000000BrrW-0X2m; Tue, 27 Aug 2024 15:26:24 +0000 Received: from nyc.source.kernel.org ([147.75.193.91]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1siy4Z-0000000BrWk-0Gil for linux-arm-kernel@lists.infradead.org; Tue, 27 Aug 2024 15:25:32 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 3F92AA41B10; Tue, 27 Aug 2024 15:25:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B09CEC61071; Tue, 27 Aug 2024 15:25:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1724772329; bh=euMf5tH8DhCXHxP9a0R6MM/IbJ5jecC+4Ci0Nz8ABRc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SxtuwGq5GSrbCZ0zKVS1qAIXpqujM4kQq0g7432ls49+8hye9lKbJMuLNvCHVVAM8 R4sHaA68djDpXToAI4W0fn48dGQHMpf3FzkL5zl6nwlffE556BCTbH9hmEWBMXFpml mDotR0N25K019Hmg0oTrlSVGSxAL+f7SywnEYPTRcSR5wUI+TRaDAZHkgerh1y2j1+ iDNc0HEq/8BxhH3Q/JiGZ4HSaRqXekvVinqEVaJ4SfMDxQRxofeMmaBkg8M5+Qy+u/ FiTRUmcr9JUG4/W3BS+6iwTRUST2uavjjcCuaq/QIc37xCSzKo1XWN/0CMEBUemdLF 4ArPJulv07odw== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1siy4V-007HOs-Kg; Tue, 27 Aug 2024 16:25:27 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Alexander Potapenko Subject: [PATCH v2 01/11] KVM: arm64: Move GICv3 trap configuration to kvm_calculate_traps() Date: Tue, 27 Aug 2024 16:25:07 +0100 Message-Id: <20240827152517.3909653-2-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240827152517.3909653-1-maz@kernel.org> References: <20240827152517.3909653-1-maz@kernel.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, glider@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240827_082531_258590_2271FFDB X-CRM114-Status: GOOD ( 13.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Follow the pattern introduced with vcpu_set_hcr(), and introduce vcpu_set_ich_hcr(), which configures the GICv3 traps at the same point. This will allow future changes to introduce trap configuration on a per-VM basis. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/sys_regs.c | 1 + arch/arm64/kvm/vgic/vgic-v3.c | 9 +++++++++ arch/arm64/kvm/vgic/vgic.h | 2 ++ 3 files changed, 12 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 31e49da867ff..257c8da23a4e 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -4551,6 +4551,7 @@ void kvm_calculate_traps(struct kvm_vcpu *vcpu) mutex_lock(&kvm->arch.config_lock); vcpu_set_hcr(vcpu); + vcpu_set_ich_hcr(vcpu); if (cpus_have_final_cap(ARM64_HAS_HCX)) { /* diff --git a/arch/arm64/kvm/vgic/vgic-v3.c b/arch/arm64/kvm/vgic/vgic-v3.c index 3eecdd2f4b8f..11718412921f 100644 --- a/arch/arm64/kvm/vgic/vgic-v3.c +++ b/arch/arm64/kvm/vgic/vgic-v3.c @@ -292,6 +292,15 @@ void vgic_v3_enable(struct kvm_vcpu *vcpu) /* Get the show on the road... */ vgic_v3->vgic_hcr = ICH_HCR_EN; +} + +void vcpu_set_ich_hcr(struct kvm_vcpu *vcpu) +{ + struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3; + + if (!kvm_has_gicv3(vcpu->kvm)) + return; + if (group0_trap) vgic_v3->vgic_hcr |= ICH_HCR_TALL0; if (group1_trap) diff --git a/arch/arm64/kvm/vgic/vgic.h b/arch/arm64/kvm/vgic/vgic.h index 8532bfe3fed4..c72c38b44234 100644 --- a/arch/arm64/kvm/vgic/vgic.h +++ b/arch/arm64/kvm/vgic/vgic.h @@ -346,6 +346,8 @@ void vgic_v4_configure_vsgis(struct kvm *kvm); void vgic_v4_get_vlpi_state(struct vgic_irq *irq, bool *val); int vgic_v4_request_vpe_irq(struct kvm_vcpu *vcpu, int irq); +void vcpu_set_ich_hcr(struct kvm_vcpu *vcpu); + static inline bool kvm_has_gicv3(struct kvm *kvm) { return (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif) &&