@@ -595,6 +595,24 @@ static inline bool id_aa64pfr0_32bit_el0(u64 pfr0)
{
u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_EL0_SHIFT);
+#if CONFIG_ARCH_APPLE
+ /*
+ * The Apple A10(X) consist of logical cores that can switch between
+ * P-mode and E-mode based on the frequency. Only the P-mode supports
+ * 32-bit EL0. Pretend that the CPU does not support 32-bit EL0.
+ */
+
+ static const struct midr_range hurricane_zephyr_list[] = {
+ MIDR_ALL_VERSIONS(MIDR_APPLE_A10_T2_HURRICANE_ZEPHYR),
+ MIDR_ALL_VERSIONS(MIDR_APPLE_A10X_HURRICANE_ZEPHYR),
+ {}
+ };
+
+ if (is_midr_in_range_list(read_cpuid_id(), hurricane_zephyr_list))
+ return false;
+
+#endif
+
return val == ID_AA64PFR0_EL1_EL0_AARCH32;
}
@@ -129,18 +129,20 @@
#define HISI_CPU_PART_TSV110 0xD01
-#define APPLE_CPU_PART_M1_ICESTORM 0x022
-#define APPLE_CPU_PART_M1_FIRESTORM 0x023
-#define APPLE_CPU_PART_M1_ICESTORM_PRO 0x024
-#define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025
-#define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028
-#define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029
-#define APPLE_CPU_PART_M2_BLIZZARD 0x032
-#define APPLE_CPU_PART_M2_AVALANCHE 0x033
-#define APPLE_CPU_PART_M2_BLIZZARD_PRO 0x034
-#define APPLE_CPU_PART_M2_AVALANCHE_PRO 0x035
-#define APPLE_CPU_PART_M2_BLIZZARD_MAX 0x038
-#define APPLE_CPU_PART_M2_AVALANCHE_MAX 0x039
+#define APPLE_CPU_PART_A10_T2_HURRICANE_ZEPHYR 0x6
+#define APPLE_CPU_PART_A10X_HURRICANE_ZEPHYR 0x7
+#define APPLE_CPU_PART_M1_ICESTORM 0x022
+#define APPLE_CPU_PART_M1_FIRESTORM 0x023
+#define APPLE_CPU_PART_M1_ICESTORM_PRO 0x024
+#define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025
+#define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028
+#define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029
+#define APPLE_CPU_PART_M2_BLIZZARD 0x032
+#define APPLE_CPU_PART_M2_AVALANCHE 0x033
+#define APPLE_CPU_PART_M2_BLIZZARD_PRO 0x034
+#define APPLE_CPU_PART_M2_AVALANCHE_PRO 0x035
+#define APPLE_CPU_PART_M2_BLIZZARD_MAX 0x038
+#define APPLE_CPU_PART_M2_AVALANCHE_MAX 0x039
#define AMPERE_CPU_PART_AMPERE1 0xAC3
@@ -199,6 +201,8 @@
#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
+#define MIDR_APPLE_A10_T2_HURRICANE_ZEPHYR MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_A10_T2_HURRICANE_ZEPHYR)
+#define MIDR_APPLE_A10X_HURRICANE_ZEPHYR MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_A10X_HURRICANE_ZEPHYR)
#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
#define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
#define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO)
The Apple A10(X) consists of logical cores that can switch between P-mode and E-mode based on the frequency. However, only P-mode supported 32-bit EL0. Trying to support 32-bit EL0 on a CPU that can only execute it in certain states is a bad idea. The A10(X) only supports 16KB page size anyway so many AArch32 executables won't run anyways. Pretend that it does not support 32-bit EL0 at all. Note that this patch does not make sense without [1]. [1]: https://lore.kernel.org/asahi/20240829092610.89731-1-towinchenmi@gmail.com Signed-off-by: Nick Chan <towinchenmi@gmail.com> --- arch/arm64/include/asm/cpufeature.h | 18 ++++++++++++++++++ arch/arm64/include/asm/cputype.h | 28 ++++++++++++++++------------ 2 files changed, 34 insertions(+), 12 deletions(-)