| Message ID | 20240830130218.3377060-6-claudiu.beznea.uj@bp.renesas.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add RTC support for the Renesas RZ/G3S SoC | expand |
On Fri, 30 Aug 2024 16:02:11 +0300, Claudiu wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Document the RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC. > The RTC IP available on Renesas RZ/V2H is almost identical with the > one found on Renesas RZ/G3S (it misses the time capture functionality > which is not yet implemented on proposed driver). For this, added also a > generic compatible that will be used at the moment as fallback for both > RZ/G3S and RZ/V2H. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > --- > > Changes in v3: > - added RTC bus clock, reset and power-domain; it has been detected > by reverse engineering that RTC and VBATTB clock, reset and power > domain are shared; HW manual doesn't mention it > - updated example with these and with assigned-clock properties > needed to configure the VBATTCLK MUX with proper parent > - updated example section with dt-bindings/clock/r9a08g045-cpg.h > and dt-bindings/clock/r9a08g045-vbattb.h includes > - for all these, dropped Conor's Rb tag > > Changes in v2: > - updated patch description and title > - included reference to rtc.yaml > - updated compatible list with a generic compatible as explained in > patch description; with this the node in examples section has also been > updated > - used items to describe interrupts, interrupt-names, clock, clock-names > - updated title section > > .../bindings/rtc/renesas,rz-rtca3.yaml | 86 +++++++++++++++++++ > 1 file changed, 86 insertions(+) > create mode 100644 Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml > Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml new file mode 100644 index 000000000000..bc99795dfb6b --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/renesas,rz-rtca3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RTCA-3 Real Time Clock + +maintainers: + - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + items: + - enum: + - renesas,r9a08g045-rtca3 # RZ/G3S + - const: renesas,rz-rtca3 + + reg: + maxItems: 1 + + interrupts: + items: + - description: Alarm interrupt + - description: Periodic interrupt + - description: Carry interrupt + + interrupt-names: + items: + - const: alarm + - const: period + - const: carry + + clocks: + items: + - description: RTC bus clock + - description: RTC counter clock + + clock-names: + items: + - const: bus + - const: counter + + power-domains: + maxItems: 1 + + resets: + items: + - description: VBATTB module reset + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r9a08g045-cpg.h> + #include <dt-bindings/clock/r9a08g045-vbattb.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + rtc@1004ec00 { + compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; + reg = <0x1004ec00 0x400>; + interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "alarm", "period", "carry"; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattclk VBATTB_VBATTCLK>; + clock-names = "bus", "counter"; + assigned-clocks = <&vbattb VBATTB_MUX>; + assigned-clock-parents = <&vbattb VBATTB_XC>; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + };