From patchwork Fri Aug 30 16:17:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Beleswar Prasad Padhi X-Patchwork-Id: 13785337 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5971FCA100A for ; Fri, 30 Aug 2024 16:23:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=+nWZk5H7bvoB55vHrKYWMBxW4eVVWqOq41u+HHflULw=; b=ve+M+ZeZ/lWsLBZvoyFBN2YVxe yFiGNyX8LF5Us/1i36n1T7OwR3oXD+uv4p/pb0gpPXo+bJKEytZzaaN74EHRjuGuhCDmkKpPnwbRo nzONH1A+wIUIGUYFCDL6RfChjtY9LFAtuBuPrCFnyl/WiS22W23ImOy1r69ZrEdlBV12ljFRMDvQ4 V//w9uZb5JiSPYayRk+IXiwCsXguSAW3SoCUepcyXrq07LTm5G/1yjV+I1ZlhLtYMblE/0JwkjKjR c1uTmjvIaxnKEGrF+PH0fivR+pijz153lZaUY/Cni8rpqc8ilosGv05VKrhAIY0rnFbF2Al6EgjBT W4Tq7k3A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sk4P4-0000000705M-1034; Fri, 30 Aug 2024 16:23:14 +0000 Received: from fllv0015.ext.ti.com ([198.47.19.141]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sk4Jy-00000006z3h-1efc for linux-arm-kernel@lists.infradead.org; Fri, 30 Aug 2024 16:18:00 +0000 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 47UGHswG066831; Fri, 30 Aug 2024 11:17:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1725034674; bh=+nWZk5H7bvoB55vHrKYWMBxW4eVVWqOq41u+HHflULw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=KgSIGDYSq0tmMGanKHRcBXHAIxtsw6V9Ty08/3GqvX7KrxsNFo/kjAJnF6k07cRb8 Th8Fse7sNeBc/52yDURD1C7jExf0GjNkPpkolwVk6qJh4eWrNYo35r2Nbo16iys3ZB e9l4wFkCczi1fodX4vGilSqkYON3x8+r9ILAUwWc= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 47UGHsIJ024652 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 30 Aug 2024 11:17:54 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 30 Aug 2024 11:17:54 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 30 Aug 2024 11:17:54 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.227.151]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 47UGHhRc103243; Fri, 30 Aug 2024 11:17:51 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , Subject: [PATCH v5 2/2] arm64: dts: ti: k3-j722s-evm: Enable Inter-Processor Communication Date: Fri, 30 Aug 2024 21:47:42 +0530 Message-ID: <20240830161742.925145-3-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240830161742.925145-1-b-padhi@ti.com> References: <20240830161742.925145-1-b-padhi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240830_091758_570704_2E8103E8 X-CRM114-Status: GOOD ( 14.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Apurva Nandan The K3 J722S-EVM platform is based on the J722S SoC which has one single-core Arm Cortex-R5F processor in each of the WAKEUP, MCU and MAIN voltage domain, and two C71x DSP subsystems in MAIN voltage domain. The Inter-Processor communication between the A53 cores and these R5F and DSP remote cores is achieved through shared memory and Mailboxes. Thus, add the memory carveouts and enable the mailbox clusters required for communication. Also, The remoteproc firmware like of R5F and DSPs in the MAIN voltage domain use timers. Therefore, change the status of the timer nodes to "reserved" to avoid any clash during booting of remotecores. Usage is described as below: +===================+=============+ | Remoteproc Node | Timer Node | +===================+=============+ | main_r5fss0_core0 | main_timer0 | +-------------------+-------------+ | c7x_0 | main_timer1 | +-------------------+-------------+ | c7x_1 | main_timer2 | +-------------------+-------------+ Signed-off-by: Apurva Nandan [ Enabled mailbox instances and Reserved timer nodes ] Signed-off-by: Beleswar Padhi Reviewed-by: Udit Kumar --- v5: Changelog: 1) Updated commit message to correctly reflect the host core name (A53 not A72). 2) Updated mbox DT node label and name to "mbox_wkup_r5_0" from "mbox_r5_0" for clarity. Link to v4: https://lore.kernel.org/all/20240829060932.3441295-3-b-padhi@ti.com/ v4: Changelog: 1) Moved "status" property to the end in all the extended DT nodes added in this patch. 2) Preceded child-nodes by a single blank line in the extended DT nodes added in this patch. Link to v3: https://lore.kernel.org/all/20240828112713.2668526-3-b-padhi@ti.com/ v3: Changelog: 1) Reserved conflicting timer nodes with remoteproc firmware (reflected the same in commit message). 2) Simplified $subject to clarify that this patch enables IPC and transferred the details into commit message. Link to v2: https://lore.kernel.org/all/20240612112259.1131653-3-b-padhi@ti.com/ v2: Changelog: 1) Squashed Patch 2 and 3 from V1 into Patch 2 in V2 as they were doing the same logical thing. Links to v1: https://lore.kernel.org/all/20240607090433.488454-3-b-padhi@ti.com/ https://lore.kernel.org/all/20240607090433.488454-4-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 157 ++++++++++++++++++++++++ 1 file changed, 157 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index 41c36f82a3c5..a00f4a7d20d9 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -52,12 +52,71 @@ secure_ddr: optee@9e800000 { no-map; }; + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + c7x_0_dma_memory_region: c7x-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: c7x-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + c7x_1_dma_memory_region: c7x-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + c7x_1_memory_region: c7x-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a5000000 { + reg = <0x00 0xa5000000 0x00 0x1c00000>; + alignment = <0x1000>; + no-map; + }; }; vmain_pd: regulator-0 { @@ -558,6 +617,104 @@ &sdhci1 { bootph-all; }; +&mailbox0_cluster0 { + status = "okay"; + + mbox_wkup_r5_0: mbox-wkup-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster3 { + status = "okay"; + + mbox_main_r5_0: mbox-main-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c7x_1: mbox-c7x-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +/* Timers are used by Remoteproc firmware */ +&main_timer0 { + status = "reserved"; +}; + +&main_timer1 { + status = "reserved"; +}; + +&main_timer2 { + status = "reserved"; +}; + +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_wkup_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&main_r5fss0 { + status = "okay"; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&c7x_0 { + mboxes = <&mailbox0_cluster2 &mbox_c7x_0>; + memory-region = <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; + status = "okay"; +}; + +&c7x_1 { + mboxes = <&mailbox0_cluster3 &mbox_c7x_1>; + memory-region = <&c7x_1_dma_memory_region>, + <&c7x_1_memory_region>; + status = "okay"; +}; + &serdes_ln_ctrl { idle-states = , ;