[2/7] clk: en7523: set REG_PCIE*_{MEM,MEM_MASK} via syscon

Commit Message

Lorenzo Bianconi Aug. 31, 2024, 7:18 a.m. UTC

REG_PCIE*_MEM and REG_PCIE*_MEM_MASK memory regions (PBUS_CSR) are not
part of the scu block on the EN7581 SoC, so configure them via a dedicated
syscon node. This patch does not introduce any backward incompatibility
since the dts for EN7581 SoC is not public yet.

Signed-off-by: Lorenzo Bianconi <[e-mail]>
---
 drivers/clk/clk-en7523.c | 24 +++++++++++++-----------
 1 file changed, 13 insertions(+), 11 deletions(-)

Comments

Conor Dooley Sept. 2, 2024, 8:21 a.m. UTC | #1

On Sat, Aug 31, 2024 at 09:18:44AM +0200, Lorenzo Bianconi wrote:
> +	map = syscon_regmap_lookup_by_compatible("airoha,en7581-pbus-csr");

Is this compatible documented? (On a laptop in an airport with no recent
kernel tree, so I had to resort to searching on github which turned up
nothing).

Lorenzo Bianconi Sept. 2, 2024, 8:40 a.m. UTC | #2

> On Sat, Aug 31, 2024 at 09:18:44AM +0200, Lorenzo Bianconi wrote:
> > +	map = syscon_regmap_lookup_by_compatible("airoha,en7581-pbus-csr");
> 
> Is this compatible documented? (On a laptop in an airport with no recent
> kernel tree, so I had to resort to searching on github which turned up
> nothing).

ack, I missed that. I will fix it in v2.

Regards,
Lorenzo

Patch

diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c
index 22fbea61c3dc..2bc1bf4afbed 100644
--- a/drivers/clk/clk-en7523.c
+++ b/drivers/clk/clk-en7523.c
@@ -3,8 +3,10 @@ 
 #include <linux/delay.h>
 #include <linux/clk-provider.h>
 #include <linux/io.h>
+#include <linux/mfd/syscon.h>
 #include <linux/platform_device.h>
 #include <linux/property.h>
+#include <linux/regmap.h>
 #include <linux/reset-controller.h>
 #include <dt-bindings/clock/en7523-clk.h>
 #include <dt-bindings/reset/airoha,en7581-reset.h>
@@ -415,25 +417,25 @@  static void en7581_pci_disable(struct clk_hw *hw)
 static int en7581_clk_hw_init(struct platform_device *pdev,
 			      void __iomem *np_base)
 {
-	void __iomem *pb_base;
+	struct regmap *map;
 	u32 val;
 
-	pb_base = devm_platform_ioremap_resource(pdev, 3);
-	if (IS_ERR(pb_base))
-		return PTR_ERR(pb_base);
-
 	val = readl(np_base + REG_NP_SCU_SSTR);
 	val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK);
 	writel(val, np_base + REG_NP_SCU_SSTR);
 	val = readl(np_base + REG_NP_SCU_PCIC);
 	writel(val | 3, np_base + REG_NP_SCU_PCIC);
 
-	writel(0x20000000, pb_base + REG_PCIE0_MEM);
-	writel(0xfc000000, pb_base + REG_PCIE0_MEM_MASK);
-	writel(0x24000000, pb_base + REG_PCIE1_MEM);
-	writel(0xfc000000, pb_base + REG_PCIE1_MEM_MASK);
-	writel(0x28000000, pb_base + REG_PCIE2_MEM);
-	writel(0xfc000000, pb_base + REG_PCIE2_MEM_MASK);
+	map = syscon_regmap_lookup_by_compatible("airoha,en7581-pbus-csr");
+	if (IS_ERR(map))
+		return PTR_ERR(map);
+
+	regmap_write(map, REG_PCIE0_MEM, 0x20000000);
+	regmap_write(map, REG_PCIE0_MEM_MASK, 0xfc000000);
+	regmap_write(map, REG_PCIE1_MEM, 0x24000000);
+	regmap_write(map, REG_PCIE1_MEM_MASK, 0xfc000000);
+	regmap_write(map, REG_PCIE2_MEM, 0x28000000);
+	regmap_write(map, REG_PCIE2_MEM_MASK, 0xfc000000);
 
 	return 0;
 }