From patchwork Tue Sep 3 21:39:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13789341 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 23F5DCD3440 for ; Tue, 3 Sep 2024 21:43:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=/6ls89eryH+yqZiBpN55UccRetM2HOH66DmUKAxp60w=; b=epy7nYMquoBYNdN6LYYMki9QQb 4VPPwSME5l8szB+s84o9HHnXXwjZaTEaX/CZKyQM41DcnM4nu4nLAOsMOVKSfEKmpGjhB+WwNVrM/ bn1Mb9cdNCIITs3B2oINIDKyHQmlEwYgk4pGJV3ODbSXuohvsq1rkE8yHc2qx0iDqOdkgbgHB4+OE d2PeS25HoQ1vpb6WFAvsbKeIGWZB6rFcqaCaJQxyDuiFIukKWSxLfF08S9avA9PQQNjCo2g/b0lb1 q4P2ZKht1+GhJo28swWd+v4KIpouE4KyesFUFX4H2S8o0Dl+cyCxIfV67yejcHuakOMWjH+UnX846 1Hgh89eA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1slbIk-0000000223K-3OQE; Tue, 03 Sep 2024 21:43:02 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1slbG5-000000021RC-2QFd for linux-arm-kernel@lists.infradead.org; Tue, 03 Sep 2024 21:40:19 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 622C45C5683; Tue, 3 Sep 2024 21:40:13 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1BE56C4CEC7; Tue, 3 Sep 2024 21:40:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725399616; bh=cGV5szsD+4z0z0sEdE3fe/LJ1oug+CG6EBmlovNucZo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=RnlwPQE4WIP8cB21O/+sbHvXFbBuusAQEkIvC3DPSg6bKQUPM29Vw0knufz17EzTZ yoa7+AgoLJQqu7GWfPQOMSEz57S9KjlGWL8u1jvJyI5dACNC3cfYDfrytYGDLquhym i4QKwhzCHVuYzPetWNlTFvh7JGRsptdqvPxoZNXyl1tCbw1R9E/9o2783uastdwXlG sqysILn+W6mP+Tu1gnVuMQhddYSbqYxbH+f528rzup6TDmHEkQ8hOyN0EUCKAm9i3o 0RkOabdAaIbMjuU8YEgTwL6DIDdzaEUxyEptvpS88bc2/fyH60NSOgL+1+q8p4F6SV sdXEtgGWwNlDA== From: Lorenzo Bianconi Date: Tue, 03 Sep 2024 23:39:46 +0200 Subject: [PATCH v2 2/7] clk: en7523: remove REG_PCIE*_{MEM,MEM_MASK} configuration MIME-Version: 1.0 Message-Id: <20240903-clk-en7581-syscon-v2-2-86fbe2fc15c3@kernel.org> References: <20240903-clk-en7581-syscon-v2-0-86fbe2fc15c3@kernel.org> In-Reply-To: <20240903-clk-en7581-syscon-v2-0-86fbe2fc15c3@kernel.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felix Fietkau , Philipp Zabel Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, upstream@airoha.com, angelogioacchino.delregno@collabora.com, linux-arm-kernel@lists.infradead.org, lorenzo.bianconi83@gmail.com, ansuelsmth@gmail.com, Lorenzo Bianconi X-Mailer: b4 0.14.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240903_144017_703455_0BBC8BAA X-CRM114-Status: GOOD ( 13.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org REG_PCIE*_MEM and REG_PCIE*_MEM_MASK regs (PBUS_CSR memory region) are not part of the scu block on the EN7581 SoC and they are used to select the PCIE ports on the PBUS, so remove this configuration from the clock driver and set these registers in the PCIE host driver instead. This patch does not introduce any backward incompatibility since the dts for EN7581 SoC is not upstream yet. Signed-off-by: Lorenzo Bianconi --- drivers/clk/clk-en7523.c | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 22fbea61c3dc..ec6716844fdc 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -31,12 +31,6 @@ #define REG_RESET_CONTROL_PCIE1 BIT(27) #define REG_RESET_CONTROL_PCIE2 BIT(26) /* EN7581 */ -#define REG_PCIE0_MEM 0x00 -#define REG_PCIE0_MEM_MASK 0x04 -#define REG_PCIE1_MEM 0x08 -#define REG_PCIE1_MEM_MASK 0x0c -#define REG_PCIE2_MEM 0x10 -#define REG_PCIE2_MEM_MASK 0x14 #define REG_NP_SCU_PCIC 0x88 #define REG_NP_SCU_SSTR 0x9c #define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13) @@ -415,26 +409,14 @@ static void en7581_pci_disable(struct clk_hw *hw) static int en7581_clk_hw_init(struct platform_device *pdev, void __iomem *np_base) { - void __iomem *pb_base; u32 val; - pb_base = devm_platform_ioremap_resource(pdev, 3); - if (IS_ERR(pb_base)) - return PTR_ERR(pb_base); - val = readl(np_base + REG_NP_SCU_SSTR); val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); writel(val, np_base + REG_NP_SCU_SSTR); val = readl(np_base + REG_NP_SCU_PCIC); writel(val | 3, np_base + REG_NP_SCU_PCIC); - writel(0x20000000, pb_base + REG_PCIE0_MEM); - writel(0xfc000000, pb_base + REG_PCIE0_MEM_MASK); - writel(0x24000000, pb_base + REG_PCIE1_MEM); - writel(0xfc000000, pb_base + REG_PCIE1_MEM_MASK); - writel(0x28000000, pb_base + REG_PCIE2_MEM); - writel(0xfc000000, pb_base + REG_PCIE2_MEM_MASK); - return 0; }