diff mbox series

[v2,7/7] arm64: dts: freescale: imx95-19x19-evk: add lpi2c[5,6] and sub-nodes

Message ID 20240903-imx95-dts-new-v2-7-8ed795d61358@nxp.com (mailing list archive)
State New, archived
Headers show
Series arm64: dts: freescale: imx95: add various nodes | expand

Commit Message

Peng Fan (OSS) Sept. 3, 2024, 7:17 a.m. UTC 
From: Peng Fan <peng.fan@nxp.com>

Add LPI2C[5,6] and the gpio expander subnodes.
Since we are at here, also add the alias for all lpi2c and gpio nodes.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 69 +++++++++++++++++++++++
 1 file changed, 69 insertions(+)

Comments

Alexander Stein Sept. 5, 2024, 12:26 p.m. UTC | #1 
Hi,

Am Dienstag, 3. September 2024, 09:17:52 CEST schrieb Peng Fan (OSS):
> From: Peng Fan <peng.fan@nxp.com>
> 
> Add LPI2C[5,6] and the gpio expander subnodes.
> Since we are at here, also add the alias for all lpi2c and gpio nodes.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 69 +++++++++++++++++++++++
>  1 file changed, 69 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
> index 5101cd171e09..6086cb7fa5a0 100644
> --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
> @@ -22,6 +22,19 @@ / {
>  	compatible = "fsl,imx95-19x19-evk", "fsl,imx95";
>  
>  	aliases {
> +		gpio0 = &gpio1;
> +		gpio1 = &gpio2;
> +		gpio2 = &gpio3;
> +		gpio3 = &gpio4;
> +		gpio4 = &gpio5;
> +		i2c0 = &lpi2c1;
> +		i2c1 = &lpi2c2;
> +		i2c2 = &lpi2c3;
> +		i2c3 = &lpi2c4;
> +		i2c4 = &lpi2c5;
> +		i2c5 = &lpi2c6;
> +		i2c6 = &lpi2c7;
> +		i2c7 = &lpi2c8;

This seems to be something for the SoC imx95.dtsi, no?

Best regards,
Alexander

>  		mmc0 = &usdhc1;
>  		mmc1 = &usdhc2;
>  		serial0 = &lpuart1;
> @@ -241,6 +254,42 @@ i2c4_gpio_expander_21: gpio@21 {
>  	};
>  };
>  
> +&lpi2c5 {
> +	clock-frequency = <100000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_lpi2c5>;
> +	status = "okay";
> +
> +	i2c5_pcal6408: gpio@21 {
> +		compatible = "nxp,pcal6408";
> +		reg = <0x21>;
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		vcc-supply = <&reg_3p3v>;
> +	};
> +};
> +
> +&lpi2c6 {
> +	clock-frequency = <100000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_lpi2c6>;
> +	status = "okay";
> +
> +	i2c6_pcal6416: gpio@21 {
> +		compatible = "nxp,pcal6416";
> +		reg = <0x21>;
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&gpio4>;
> +		interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_pcal6416>;
> +		vcc-supply = <&reg_3p3v>;
> +	};
> +};
> +
>  &lpi2c7 {
>  	clock-frequency = <1000000>;
>  	pinctrl-names = "default";
> @@ -427,6 +476,20 @@ IMX95_PAD_GPIO_IO31__LPI2C4_SCL			0x40000b9e
>  		>;
>  	};
>  
> +	pinctrl_lpi2c5: lpi2c5grp {
> +		fsl,pins = <
> +			IMX95_PAD_GPIO_IO22__LPI2C5_SDA			0x40000b9e
> +			IMX95_PAD_GPIO_IO23__LPI2C5_SCL			0x40000b9e
> +		>;
> +	};
> +
> +	pinctrl_lpi2c6: lpi2c6grp {
> +		fsl,pins = <
> +			IMX95_PAD_GPIO_IO02__LPI2C6_SDA			0x40000b9e
> +			IMX95_PAD_GPIO_IO03__LPI2C6_SCL			0x40000b9e
> +		>;
> +	};
> +
>  	pinctrl_lpi2c7: lpi2c7grp {
>  		fsl,pins = <
>  			IMX95_PAD_GPIO_IO08__LPI2C7_SDA			0x40000b9e
> @@ -446,6 +509,12 @@ IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B		0x4000031e
>  		>;
>  	};
>  
> +	pinctrl_pcal6416: pcal6416grp {
> +		fsl,pins = <
> +			IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28			0x31e
> +		>;
> +	};
> +
>  	pinctrl_pdm: pdmgrp {
>  		fsl,pins = <
>  			IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK				0x31e
> 
>
Peng Fan Sept. 6, 2024, 8:17 a.m. UTC | #2 
> Subject: Re: [PATCH v2 7/7] arm64: dts: freescale: imx95-19x19-evk:
> add lpi2c[5, 6] and sub-nodes
> 
> Hi,
> 
> Am Dienstag, 3. September 2024, 09:17:52 CEST schrieb Peng Fan
> (OSS):
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > Add LPI2C[5,6] and the gpio expander subnodes.
> > Since we are at here, also add the alias for all lpi2c and gpio nodes.
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 69
> > +++++++++++++++++++++++
> >  1 file changed, 69 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
> > b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
> > index 5101cd171e09..6086cb7fa5a0 100644
> > --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
> > @@ -22,6 +22,19 @@ / {
> >  	compatible = "fsl,imx95-19x19-evk", "fsl,imx95";
> >
> >  	aliases {
> > +		gpio0 = &gpio1;
> > +		gpio1 = &gpio2;
> > +		gpio2 = &gpio3;
> > +		gpio3 = &gpio4;
> > +		gpio4 = &gpio5;
> > +		i2c0 = &lpi2c1;
> > +		i2c1 = &lpi2c2;
> > +		i2c2 = &lpi2c3;
> > +		i2c3 = &lpi2c4;
> > +		i2c4 = &lpi2c5;
> > +		i2c5 = &lpi2c6;
> > +		i2c6 = &lpi2c7;
> > +		i2c7 = &lpi2c8;
> 
> This seems to be something for the SoC imx95.dtsi, no?

No. alias are preferred per board usage.

Regards,
Peng.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
index 5101cd171e09..6086cb7fa5a0 100644
--- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
@@ -22,6 +22,19 @@  / {
 	compatible = "fsl,imx95-19x19-evk", "fsl,imx95";
 
 	aliases {
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+		i2c0 = &lpi2c1;
+		i2c1 = &lpi2c2;
+		i2c2 = &lpi2c3;
+		i2c3 = &lpi2c4;
+		i2c4 = &lpi2c5;
+		i2c5 = &lpi2c6;
+		i2c6 = &lpi2c7;
+		i2c7 = &lpi2c8;
 		mmc0 = &usdhc1;
 		mmc1 = &usdhc2;
 		serial0 = &lpuart1;
@@ -241,6 +254,42 @@  i2c4_gpio_expander_21: gpio@21 {
 	};
 };
 
+&lpi2c5 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c5>;
+	status = "okay";
+
+	i2c5_pcal6408: gpio@21 {
+		compatible = "nxp,pcal6408";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		vcc-supply = <&reg_3p3v>;
+	};
+};
+
+&lpi2c6 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c6>;
+	status = "okay";
+
+	i2c6_pcal6416: gpio@21 {
+		compatible = "nxp,pcal6416";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pcal6416>;
+		vcc-supply = <&reg_3p3v>;
+	};
+};
+
 &lpi2c7 {
 	clock-frequency = <1000000>;
 	pinctrl-names = "default";
@@ -427,6 +476,20 @@  IMX95_PAD_GPIO_IO31__LPI2C4_SCL			0x40000b9e
 		>;
 	};
 
+	pinctrl_lpi2c5: lpi2c5grp {
+		fsl,pins = <
+			IMX95_PAD_GPIO_IO22__LPI2C5_SDA			0x40000b9e
+			IMX95_PAD_GPIO_IO23__LPI2C5_SCL			0x40000b9e
+		>;
+	};
+
+	pinctrl_lpi2c6: lpi2c6grp {
+		fsl,pins = <
+			IMX95_PAD_GPIO_IO02__LPI2C6_SDA			0x40000b9e
+			IMX95_PAD_GPIO_IO03__LPI2C6_SCL			0x40000b9e
+		>;
+	};
+
 	pinctrl_lpi2c7: lpi2c7grp {
 		fsl,pins = <
 			IMX95_PAD_GPIO_IO08__LPI2C7_SDA			0x40000b9e
@@ -446,6 +509,12 @@  IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B		0x4000031e
 		>;
 	};
 
+	pinctrl_pcal6416: pcal6416grp {
+		fsl,pins = <
+			IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28			0x31e
+		>;
+	};
+
 	pinctrl_pdm: pdmgrp {
 		fsl,pins = <
 			IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK				0x31e