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Wed, 4 Sep 2024 08:35:17 GMT Received: from jingyw-gv.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 4 Sep 2024 01:35:09 -0700 From: Jingyi Wang Date: Wed, 4 Sep 2024 16:33:49 +0800 Subject: [PATCH 08/19] dt-bindings: qcom,pdc: document QCS8300 Power Domain Controller MIME-Version: 1.0 Message-ID: <20240904-qcs8300_initial_dtsi-v1-8-d0ea9afdc007@quicinc.com> References: <20240904-qcs8300_initial_dtsi-v1-0-d0ea9afdc007@quicinc.com> In-Reply-To: <20240904-qcs8300_initial_dtsi-v1-0-d0ea9afdc007@quicinc.com> To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Bartosz Golaszewski" , Vinod Koul , Kishon Vijay Abraham I , Manivannan Sadhasivam , Alim Akhtar , Avri Altman , Bart Van Assche , "Andy Gross" , Ulf Hansson , "Thomas Gleixner" , Will Deacon , Robin Murphy , Joerg Roedel , Konrad Dybcio , Robert Marko , Das Srinagesh , Jassi Brar , Lee Jones , Srinivas Kandagatla , Catalin Marinas CC: , , , , , , , , , Jingyi Wang X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; 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PDC is included in QCS8300 SoC. This controller acts as an interrupt controller, enabling the detection of interrupts when the GIC is non-operational. Signed-off-by: Jingyi Wang --- Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml index 985fa10abb99..acd6341e9f90 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -26,6 +26,7 @@ properties: compatible: items: - enum: + - qcom,qcs8300-pdc - qcom,qdu1000-pdc - qcom,sa8775p-pdc - qcom,sc7180-pdc