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[93.198.143.118]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a8a61fbaf77sm107827666b.39.2024.09.05.02.06.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 02:06:57 -0700 (PDT) From: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= To: Fabrice Gasnier , linux-pwm@vger.kernel.org Cc: Maxime Coquelin , Alexandre Torgue , linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH] pwm: stm32: Use the right CCxNP bit in stm32_pwm_enable() Date: Thu, 5 Sep 2024 11:06:24 +0200 Message-ID: <20240905090627.197536-2-u.kleine-koenig@baylibre.com> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1511; i=u.kleine-koenig@baylibre.com; h=from:subject; bh=9YAv06fWG26oklo9XdJghSD4Pq6gsCOwAPUQlIpjLWc=; b=owEBbQGS/pANAwAKAY+A+1h9Ev5OAcsmYgBm2XSTO2fuoUly3bf3CcnfPnw65cjTrC1kFih7w 70NCDxDEy+JATMEAAEKAB0WIQQ/gaxpOnoeWYmt/tOPgPtYfRL+TgUCZtl0kwAKCRCPgPtYfRL+ TkXxB/9k3jZR9QzT8q4GtLtVtIwb1PFWDvqB+N0lA5tphTB5aoqeaEuFra/CzE7hy0C0PgKPtIG 5SLugAFZukofLefe4TsoriqxVT6svyUgOSBZNUdzRpwG7QjcD1+guffh0d2L9phVROZXX+IO6PC 4/7dk8xiuP6pYqe+QVdWX1GBhQLBqbpnt95Zxvlz25khvECFI7tkU0o7bz0hBmDer71e3I/08pt p+GztrpUeY6/envxBziXn7FumPCfu8uL/VcOwQ9ytDDeNfEmKiZ6+ZtePsArEAm9Eij9wsi1o2q CICPfk/+HJnaj/hdQXj6bZia/41Z+g8HYm7TAqhngiIMuITd X-Developer-Key: i=u.kleine-koenig@baylibre.com; a=openpgp; fpr=0D2511F322BFAB1C1580266BE2DCDD9132669BD6 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240905_020700_285755_A9ED8711 X-CRM114-Status: GOOD ( 16.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The pwm devices for a pwm_chip are numbered starting at 0, the first hw channel however has the number 1. While introducing a parametrised macro to simplify register bit usage and making that offset explicit, one of the usages was converted wrongly. This is fixed here. Fixes: 7cea05ae1d4e ("pwm-stm32: Make use of parametrised register definitions") Signed-off-by: Uwe Kleine-König Reviewed-by: Fabrice Gasnier --- Hello, during review of a patch to the stm32 pwm driver Fabrice pointed out a wrong usage of TIM_CCER_CCxNE. While (I think) we both assumed this was a problem in said patch, that problem existed already before and the proposed change just moved the problem around. So instead of (only) updating the patch later, here comes a separate fix for the driver. I intend to send this to Linus tomorrow to get it into 6.11-rc7. Best regards Uwe drivers/pwm/pwm-stm32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) base-commit: 8400291e289ee6b2bf9779ff1c83a291501f017b diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c index fd754a99cf2e..f85eb41cb084 100644 --- a/drivers/pwm/pwm-stm32.c +++ b/drivers/pwm/pwm-stm32.c @@ -412,7 +412,7 @@ static int stm32_pwm_enable(struct stm32_pwm *priv, unsigned int ch) /* Enable channel */ mask = TIM_CCER_CCxE(ch + 1); if (priv->have_complementary_output) - mask |= TIM_CCER_CCxNE(ch); + mask |= TIM_CCER_CCxNE(ch + 1); regmap_set_bits(priv->regmap, TIM_CCER, mask);