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X-CSE-ConnectionGUID: 2asziJ13SmWKAWPwHD4niQ== X-CSE-MsgGUID: /v6hnBtQRSi5YR2s2+JPHw== X-IronPort-AV: E=Sophos;i="6.10,214,1719903600"; d="scan'208";a="198959135" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 09 Sep 2024 08:15:31 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 9 Sep 2024 08:15:06 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 9 Sep 2024 08:15:04 -0700 From: Daniel Machon Date: Mon, 9 Sep 2024 17:14:45 +0200 Subject: [PATCH v2 5/9] phy: sparx5-serdes: add function for getting the CMU index MIME-Version: 1.0 Message-ID: <20240909-sparx5-lan969x-serdes-driver-v2-5-d695bcb57b84@microchip.com> References: <20240909-sparx5-lan969x-serdes-driver-v2-0-d695bcb57b84@microchip.com> In-Reply-To: <20240909-sparx5-lan969x-serdes-driver-v2-0-d695bcb57b84@microchip.com> To: Vinod Koul , Kishon Vijay Abraham I , Lars Povlsen , Steen Hegelund , , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , X-Mailer: b4 0.14-dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240909_161540_827189_5DFBA56D X-CRM114-Status: GOOD ( 12.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The SERDES to CMU mapping is different on Sparx5 and lan969x. Therefore create a function for getting the CMU index on Sparx5. Signed-off-by: Daniel Machon Reviewed-by: Steen Hegelund --- drivers/phy/microchip/sparx5_serdes.c | 11 ++--------- drivers/phy/microchip/sparx5_serdes.h | 9 +++++++++ 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/phy/microchip/sparx5_serdes.c b/drivers/phy/microchip/sparx5_serdes.c index b1376a142b14..5b918a2716dd 100644 --- a/drivers/phy/microchip/sparx5_serdes.c +++ b/drivers/phy/microchip/sparx5_serdes.c @@ -28,14 +28,6 @@ /* Optimal power settings from GUC */ #define SPX5_SERDES_QUIET_MODE_VAL 0x01ef4e0c -enum sparx5_10g28cmu_mode { - SPX5_SD10G28_CMU_MAIN = 0, - SPX5_SD10G28_CMU_AUX1 = 1, - SPX5_SD10G28_CMU_AUX2 = 3, - SPX5_SD10G28_CMU_NONE = 4, - SPX5_SD10G28_CMU_MAX, -}; - enum sparx5_sd25g28_mode_preset_type { SPX5_SD25G28_MODE_PRESET_25000, SPX5_SD25G28_MODE_PRESET_10000, @@ -1648,7 +1640,7 @@ static int sparx5_sd10g28_apply_params(struct sparx5_serdes_macro *macro, if (params->skip_cmu_cfg) return 0; - cmu_idx = sparx5_serdes_cmu_get(params->cmu_sel, lane_index); + cmu_idx = priv->data->ops.serdes_cmu_get(params->cmu_sel, macro->sidx); err = sparx5_cmu_cfg(priv, cmu_idx); if (err) return err; @@ -2520,6 +2512,7 @@ static const struct sparx5_serdes_match_data sparx5_desc = { }, .ops = { .serdes_type_set = &sparx5_serdes_type_set, + .serdes_cmu_get = &sparx5_serdes_cmu_get, }, }; diff --git a/drivers/phy/microchip/sparx5_serdes.h b/drivers/phy/microchip/sparx5_serdes.h index 785c7fe0bbeb..a7e92c1330e9 100644 --- a/drivers/phy/microchip/sparx5_serdes.h +++ b/drivers/phy/microchip/sparx5_serdes.h @@ -26,6 +26,14 @@ enum sparx5_serdes_mode { SPX5_SD_MODE_SFI, }; +enum sparx5_10g28cmu_mode { + SPX5_SD10G28_CMU_MAIN = 0, + SPX5_SD10G28_CMU_AUX1 = 1, + SPX5_SD10G28_CMU_AUX2 = 3, + SPX5_SD10G28_CMU_NONE = 4, + SPX5_SD10G28_CMU_MAX, +}; + struct sparx5_serdes_macro { struct sparx5_serdes_private *priv; u32 sidx; @@ -44,6 +52,7 @@ struct sparx5_serdes_consts { struct sparx5_serdes_ops { void (*serdes_type_set)(struct sparx5_serdes_macro *macro, int sidx); + int (*serdes_cmu_get)(enum sparx5_10g28cmu_mode mode, int sd_index); }; struct sparx5_serdes_match_data {