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AJvYcCVKVyP3kuA8s9NB0KbjiVZVDFTUeKD0yR5cQNVhY1d4Cpf4ORytDAWHhU1KBHC6agU8SOxfG2PVNRdD4a7UUQRw@lists.infradead.org X-Gm-Message-State: AOJu0Yw3FseECFE9FpAPP3nQSMDzDx2gSWAuM2CLjKrpWF/UhuQfmVxx tqICWZS153mMVQnqYsBibJweCyYX5rUMphZ89GnV23HXHTaK0pMlljfx7p88yQ== X-Google-Smtp-Source: AGHT+IGoS/wNfT96ErEpO6j2A4iVl+SSYkCw9fl18EPKIdICyKbSqkOSzDP41poSrNFHrcako0/RMQ== X-Received: by 2002:a17:903:22cb:b0:206:bbaa:84e9 with SMTP id d9443c01a7336-2070a7e5982mr90617095ad.47.1725880678168; Mon, 09 Sep 2024 04:17:58 -0700 (PDT) Received: from fshao-p620.tpe.corp.google.com ([2401:fa00:1:10:6647:6d5f:dd48:8f5c]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20710f1dc55sm32039745ad.186.2024.09.09.04.17.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Sep 2024 04:17:57 -0700 (PDT) From: Fei Shao To: AngeloGioacchino Del Regno , Matthias Brugger Cc: Fei Shao , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH 04/13] arm64: dts: mediatek: mt8188: Move vdec1 power domain under vdec0 Date: Mon, 9 Sep 2024 19:14:17 +0800 Message-ID: <20240909111535.528624-5-fshao@chromium.org> X-Mailer: git-send-email 2.46.0.469.g59c65b2a67-goog In-Reply-To: <20240909111535.528624-1-fshao@chromium.org> References: <20240909111535.528624-1-fshao@chromium.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240909_041758_800482_31511A39 X-CRM114-Status: GOOD ( 12.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org There are two hardware IP blocks in MT8188 video decoder pipeline: vdec-lat and vdec-core, which are powered by vdec0 and vdec1 power domains respectively. We noticed that vdec-core needs to be powered down before vdec-lat during suspend to prevent failures. It's unclear if it's an intended hardware design or due to power isolation glitch. But in any case, we observed a power-off sequence here, and it can be considered as an indirect dependency implication between the vdec0 and vdec1 domains. Given that, update vdec1 as a sub-domain of vdec0 to enforce the sequence. Also, use more specific clock names for both power domains. Signed-off-by: Fei Shao --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index dfbc50c878c4..445d30eee2a1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -1078,20 +1078,22 @@ power-domain@MT8188_POWER_DOMAIN_VPPSYS1 { #power-domain-cells = <0>; }; - power-domain@MT8188_POWER_DOMAIN_VDEC1 { - reg = ; - clocks = <&vdecsys CLK_VDEC2_LARB1>; - clock-names = "ss-vdec"; - mediatek,infracfg = <&infracfg_ao>; - #power-domain-cells = <0>; - }; - power-domain@MT8188_POWER_DOMAIN_VDEC0 { reg = ; clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>; - clock-names = "ss-vdec"; + clock-names = "ss-vdec1-soc-l1"; mediatek,infracfg = <&infracfg_ao>; - #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_VDEC1 { + reg = ; + clocks = <&vdecsys CLK_VDEC2_LARB1>; + clock-names = "ss-vdec2-l1"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; }; cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE {