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Signed-off-by: Bogdan-Gabriel Roman Signed-off-by: Ghennadi Procopciuc Signed-off-by: Ciprian Marian Costea --- .../devicetree/bindings/rtc/nxp,s32g-rtc.yaml | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/nxp,s32g-rtc.yaml diff --git a/Documentation/devicetree/bindings/rtc/nxp,s32g-rtc.yaml b/Documentation/devicetree/bindings/rtc/nxp,s32g-rtc.yaml new file mode 100644 index 000000000000..8f78bce6470a --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/nxp,s32g-rtc.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/nxp,s32g-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP S32G2/S32G3 Real Time Clock (RTC) + +maintainers: + - Bogdan Hamciuc + - Ciprian Marian Costea + +properties: + compatible: + const: nxp,s32g-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + nxp,clksel: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Input clock selector. Choose between 0-SIRC and 2-FIRC. + The reason for these IDs not being consecutive is because + they are hardware coupled. + enum: + - 0 # SIRC + - 2 # FIRC + + nxp,dividers: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + An array of two u32 elements, the former encoding DIV512, + the latter encoding DIV32. These are dividers that can be enabled + individually, or cascaded. Use 0 to disable the respective divider, + and 1 to enable it. + items: + - description: div512 + - description: div32 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: ipg + - const: sirc + - const: firc + +required: + - clock-names + - clocks + - compatible + - interrupts + - nxp,clksel + - nxp,dividers + - reg + +additionalProperties: false + +examples: + - | + #include + #include + + rtc0: rtc@40060000 { + compatible = "nxp,s32g-rtc"; + reg = <0x40060000 0x1000>; + interrupts = ; + clocks = <&clks 54>, + <&clks 55>, + <&clks 56>; + clock-names = "ipg", "sirc", "firc"; + nxp,clksel = <2>; + nxp,dividers = <1 0>; + };