| Message ID | 20240912070624.25540-1-pablo.sun@mediatek.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] arm64: dts: mediatek: mt8395-genio-1200-evk: Enable GPU | expand |
Il 12/09/24 09:06, Pablo Sun ha scritto: > Enable the Mali Valhall GPU on Genio 1200 EVK by providing regulator > supply settingsi to gpu and mfg1, and enable the GPU node. > > In addition, set the GPU related regulator voltage range: > > 1. Set the recommended input voltage range of DVDD_GPU to (0.546V-0.787V), > based on Table 5-3 of MT8395 Application Processor Datasheet. > The regulator mt6315_7_vbuck1("Vgpu") connects to the DVDD_GPU input. > Note that the minimum voltage in SoC eFuse data, which is read by > MTK-SVS to adjust the regulator voltage, does not go below > the recommended operating voltage in the datasheet. > > 2. Set the input voltage of DVDD_SRAM_GPU, supplied by > mt6359_vsram_others_ldo_reg, to 0.75V, the recommended typical > operating voltage in MT8395 Application Processor Datasheet. > > This patch is tested by enabling CONFIG_DRM_PANFROST and > on Genio 1200 EVK it probed with following dmesg: > > ``` > panfrost 13000000.gpu: clock rate = 700000092 > panfrost 13000000.gpu: mali-g57 id 0x9093 major 0x0 minor 0x1 status 0x0 > panfrost 13000000.gpu: features: 00000000,000019f7, > issues: 00000001,80000400 > panfrost 13000000.gpu: Features: L2:0x07120206 Shader:0x00000000 > Tiler:0x00000809 Mem:0x301 > MMU:0x00002830 AS:0xff JS:0x7 > panfrost 13000000.gpu: shader_present=0x50045 l2_present=0x1 > [drm] Initialized panfrost 1.2.0 for 13000000.gpu on minor 0 > ``` > > Signed-off-by: Pablo Sun <pablo.sun@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
On Thu, 12 Sep 2024 15:06:24 +0800, Pablo Sun wrote: > Enable the Mali Valhall GPU on Genio 1200 EVK by providing regulator > supply settingsi to gpu and mfg1, and enable the GPU node. > > In addition, set the GPU related regulator voltage range: > > 1. Set the recommended input voltage range of DVDD_GPU to (0.546V-0.787V), > based on Table 5-3 of MT8395 Application Processor Datasheet. > The regulator mt6315_7_vbuck1("Vgpu") connects to the DVDD_GPU input. > Note that the minimum voltage in SoC eFuse data, which is read by > MTK-SVS to adjust the regulator voltage, does not go below > the recommended operating voltage in the datasheet. > > 2. Set the input voltage of DVDD_SRAM_GPU, supplied by > mt6359_vsram_others_ldo_reg, to 0.75V, the recommended typical > operating voltage in MT8395 Application Processor Datasheet. > > This patch is tested by enabling CONFIG_DRM_PANFROST and > on Genio 1200 EVK it probed with following dmesg: > > ``` > panfrost 13000000.gpu: clock rate = 700000092 > panfrost 13000000.gpu: mali-g57 id 0x9093 major 0x0 minor 0x1 status 0x0 > panfrost 13000000.gpu: features: 00000000,000019f7, > issues: 00000001,80000400 > panfrost 13000000.gpu: Features: L2:0x07120206 Shader:0x00000000 > Tiler:0x00000809 Mem:0x301 > MMU:0x00002830 AS:0xff JS:0x7 > panfrost 13000000.gpu: shader_present=0x50045 l2_present=0x1 > [drm] Initialized panfrost 1.2.0 for 13000000.gpu on minor 0 > ``` > > Signed-off-by: Pablo Sun <pablo.sun@mediatek.com> > --- > .../dts/mediatek/mt8395-genio-1200-evk.dts | 19 +++++++++++++++++-- > 1 file changed, 17 insertions(+), 2 deletions(-) > My bot found new DTB warnings on the .dts files added or changed in this series. Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings are fixed by another series. Ultimately, it is up to the platform maintainer whether these warnings are acceptable or not. No need to reply unless the platform maintainer has comments. If you already ran DT checks and didn't see these error(s), then make sure dt-schema is up to date: pip3 install dtschema --upgrade New warnings running 'make CHECK_DTBS=y mediatek/mt8395-genio-1200-evk.dtb' for 20240912070624.25540-1-pablo.sun@mediatek.com: arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dtb: display@14f06000: clocks: [[32, 14], [32, 43], [32, 44]] is too long from schema $id: http://devicetree.org/schemas/display/mediatek/mediatek,split.yaml# arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dtb: dp-intf@1c113000: power-domains: False schema does not allow [[45, 18]] from schema $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
On 12/09/2024 09:06, Pablo Sun wrote: > Enable the Mali Valhall GPU on Genio 1200 EVK by providing regulator > supply settingsi to gpu and mfg1, and enable the GPU node. > > In addition, set the GPU related regulator voltage range: > > 1. Set the recommended input voltage range of DVDD_GPU to (0.546V-0.787V), > based on Table 5-3 of MT8395 Application Processor Datasheet. > The regulator mt6315_7_vbuck1("Vgpu") connects to the DVDD_GPU input. > Note that the minimum voltage in SoC eFuse data, which is read by > MTK-SVS to adjust the regulator voltage, does not go below > the recommended operating voltage in the datasheet. > > 2. Set the input voltage of DVDD_SRAM_GPU, supplied by > mt6359_vsram_others_ldo_reg, to 0.75V, the recommended typical > operating voltage in MT8395 Application Processor Datasheet. > > This patch is tested by enabling CONFIG_DRM_PANFROST and > on Genio 1200 EVK it probed with following dmesg: > > ``` > panfrost 13000000.gpu: clock rate = 700000092 > panfrost 13000000.gpu: mali-g57 id 0x9093 major 0x0 minor 0x1 status 0x0 > panfrost 13000000.gpu: features: 00000000,000019f7, > issues: 00000001,80000400 > panfrost 13000000.gpu: Features: L2:0x07120206 Shader:0x00000000 > Tiler:0x00000809 Mem:0x301 > MMU:0x00002830 AS:0xff JS:0x7 > panfrost 13000000.gpu: shader_present=0x50045 l2_present=0x1 > [drm] Initialized panfrost 1.2.0 for 13000000.gpu on minor 0 > ``` > > Signed-off-by: Pablo Sun <pablo.sun@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > --- > .../dts/mediatek/mt8395-genio-1200-evk.dts | 19 +++++++++++++++++-- > 1 file changed, 17 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts > index a06610fff8ad..4f7d66d6d785 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts > +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts > @@ -194,6 +194,11 @@ eth_phy0: eth-phy0@1 { > }; > }; > > +&gpu { > + mali-supply = <&mt6315_7_vbuck1>; > + status = "okay"; > +}; > + > &i2c0 { > clock-frequency = <400000>; > pinctrl-0 = <&i2c0_pins>; > @@ -337,6 +342,10 @@ &mfg0 { > domain-supply = <&mt6315_7_vbuck1>; > }; > > +&mfg1 { > + domain-supply = <&mt6359_vsram_others_ldo_reg>; > +}; > + > &mmc0 { > status = "okay"; > pinctrl-names = "default", "state_uhs"; > @@ -407,6 +416,12 @@ &mt6359_vrf12_ldo_reg { > regulator-always-on; > }; > > +/* for GPU SRAM */ > +&mt6359_vsram_others_ldo_reg { > + regulator-min-microvolt = <750000>; > + regulator-max-microvolt = <750000>; > +}; > + > &mt6359codec { > mediatek,mic-type-0 = <1>; /* ACC */ > mediatek,mic-type-1 = <3>; /* DCC */ > @@ -839,8 +854,8 @@ regulators { > mt6315_7_vbuck1: vbuck1 { > regulator-compatible = "vbuck1"; > regulator-name = "Vgpu"; > - regulator-min-microvolt = <300000>; > - regulator-max-microvolt = <1193750>; > + regulator-min-microvolt = <546000>; > + regulator-max-microvolt = <787000>; > regulator-enable-ramp-delay = <256>; > regulator-allowed-modes = <0 1 2>; > };
diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts index a06610fff8ad..4f7d66d6d785 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts @@ -194,6 +194,11 @@ eth_phy0: eth-phy0@1 { }; }; +&gpu { + mali-supply = <&mt6315_7_vbuck1>; + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; pinctrl-0 = <&i2c0_pins>; @@ -337,6 +342,10 @@ &mfg0 { domain-supply = <&mt6315_7_vbuck1>; }; +&mfg1 { + domain-supply = <&mt6359_vsram_others_ldo_reg>; +}; + &mmc0 { status = "okay"; pinctrl-names = "default", "state_uhs"; @@ -407,6 +416,12 @@ &mt6359_vrf12_ldo_reg { regulator-always-on; }; +/* for GPU SRAM */ +&mt6359_vsram_others_ldo_reg { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; +}; + &mt6359codec { mediatek,mic-type-0 = <1>; /* ACC */ mediatek,mic-type-1 = <3>; /* DCC */ @@ -839,8 +854,8 @@ regulators { mt6315_7_vbuck1: vbuck1 { regulator-compatible = "vbuck1"; regulator-name = "Vgpu"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1193750>; + regulator-min-microvolt = <546000>; + regulator-max-microvolt = <787000>; regulator-enable-ramp-delay = <256>; regulator-allowed-modes = <0 1 2>; };
Enable the Mali Valhall GPU on Genio 1200 EVK by providing regulator supply settingsi to gpu and mfg1, and enable the GPU node. In addition, set the GPU related regulator voltage range: 1. Set the recommended input voltage range of DVDD_GPU to (0.546V-0.787V), based on Table 5-3 of MT8395 Application Processor Datasheet. The regulator mt6315_7_vbuck1("Vgpu") connects to the DVDD_GPU input. Note that the minimum voltage in SoC eFuse data, which is read by MTK-SVS to adjust the regulator voltage, does not go below the recommended operating voltage in the datasheet. 2. Set the input voltage of DVDD_SRAM_GPU, supplied by mt6359_vsram_others_ldo_reg, to 0.75V, the recommended typical operating voltage in MT8395 Application Processor Datasheet. This patch is tested by enabling CONFIG_DRM_PANFROST and on Genio 1200 EVK it probed with following dmesg: ``` panfrost 13000000.gpu: clock rate = 700000092 panfrost 13000000.gpu: mali-g57 id 0x9093 major 0x0 minor 0x1 status 0x0 panfrost 13000000.gpu: features: 00000000,000019f7, issues: 00000001,80000400 panfrost 13000000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x301 MMU:0x00002830 AS:0xff JS:0x7 panfrost 13000000.gpu: shader_present=0x50045 l2_present=0x1 [drm] Initialized panfrost 1.2.0 for 13000000.gpu on minor 0 ``` Signed-off-by: Pablo Sun <pablo.sun@mediatek.com> --- .../dts/mediatek/mt8395-genio-1200-evk.dts | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-)