Message ID | 20240913145711.2284295-1-sean.anderson@linux.dev (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [net,v2] net: xilinx: axienet: Schedule NAPI in two steps | expand |
On Fri, Sep 13, 2024 at 4:57 PM Sean Anderson <sean.anderson@linux.dev> wrote: > > As advised by Documentation/networking/napi.rst, masking IRQs after > calling napi_schedule can be racy. Avoid this by only masking/scheduling > if napi_schedule_prep returns true. > > Fixes: 9e2bc267e780 ("net: axienet: Use NAPI for TX completion path") > Fixes: cc37610caaf8 ("net: axienet: implement NAPI and GRO receive") > Signed-off-by: Sean Anderson <sean.anderson@linux.dev> > Reviewed-by: Shannon Nelson <shannon.nelson@amd.com> > --- Reviewed-by: Eric Dumazet <edumazet@google.com>
Hello: This patch was applied to netdev/net.git (main) by Paolo Abeni <pabeni@redhat.com>: On Fri, 13 Sep 2024 10:57:11 -0400 you wrote: > As advised by Documentation/networking/napi.rst, masking IRQs after > calling napi_schedule can be racy. Avoid this by only masking/scheduling > if napi_schedule_prep returns true. > > Fixes: 9e2bc267e780 ("net: axienet: Use NAPI for TX completion path") > Fixes: cc37610caaf8 ("net: axienet: implement NAPI and GRO receive") > Signed-off-by: Sean Anderson <sean.anderson@linux.dev> > Reviewed-by: Shannon Nelson <shannon.nelson@amd.com> > > [...] Here is the summary with links: - [net,v2] net: xilinx: axienet: Schedule NAPI in two steps https://git.kernel.org/netdev/net/c/ba0da2dc934e You are awesome, thank you!
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c index 9eb300fc3590..3de6559ceea6 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -1222,9 +1222,10 @@ static irqreturn_t axienet_tx_irq(int irq, void *_ndev) u32 cr = lp->tx_dma_cr; cr &= ~(XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK); - axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr); - - napi_schedule(&lp->napi_tx); + if (napi_schedule_prep(&lp->napi_tx)) { + axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr); + __napi_schedule(&lp->napi_tx); + } } return IRQ_HANDLED; @@ -1266,9 +1267,10 @@ static irqreturn_t axienet_rx_irq(int irq, void *_ndev) u32 cr = lp->rx_dma_cr; cr &= ~(XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK); - axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr); - - napi_schedule(&lp->napi_rx); + if (napi_schedule_prep(&lp->napi_rx)) { + axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr); + __napi_schedule(&lp->napi_rx); + } } return IRQ_HANDLED;