@@ -113,6 +113,13 @@ config RESET_IMX8MP_AUDIOMIX
help
This enables the reset controller driver for i.MX8MP AudioMix
+config RESET_IMX8ULP_SIM
+ tristate "i.MX8ULP SIM Reset Driver"
+ depends on ARCH_MXC
+ help
+ This enables the SIM (System Integration Module) reset driver
+ for i.MX8ULP SoC.
+
config RESET_INTEL_GW
bool "Intel Reset Controller Driver"
depends on X86 || COMPILE_TEST
@@ -16,6 +16,7 @@ obj-$(CONFIG_RESET_GPIO) += reset-gpio.o
obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
obj-$(CONFIG_RESET_IMX8MP_AUDIOMIX) += reset-imx8mp-audiomix.o
+obj-$(CONFIG_RESET_IMX8ULP_SIM) += reset-imx8ulp-sim.o
obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
obj-$(CONFIG_RESET_K210) += reset-k210.o
obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
new file mode 100644
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+#include <linux/of_platform.h>
+
+#define IMX8ULP_SIM_RESET_MIPI_DSI_RST_DPI_N 0
+#define IMX8ULP_SIM_RESET_MIPI_DSI_RST_ESC_N 1
+#define IMX8ULP_SIM_RESET_MIPI_DSI_RST_BYTE_N 2
+
+#define IMX8ULP_SIM_RESET_NUM 3
+
+#define AVD_SIM_SYSCTRL0 0x8
+
+struct imx8ulp_sim_reset {
+ struct reset_controller_dev rcdev;
+ struct regmap *regmap;
+};
+
+static const u32 imx8ulp_sim_reset_bits[IMX8ULP_SIM_RESET_NUM] = {
+ [IMX8ULP_SIM_RESET_MIPI_DSI_RST_DPI_N] = BIT(3),
+ [IMX8ULP_SIM_RESET_MIPI_DSI_RST_ESC_N] = BIT(4),
+ [IMX8ULP_SIM_RESET_MIPI_DSI_RST_BYTE_N] = BIT(5),
+};
+
+static inline struct imx8ulp_sim_reset *
+to_imx8ulp_sim_reset(struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct imx8ulp_sim_reset, rcdev);
+}
+
+static int imx8ulp_sim_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct imx8ulp_sim_reset *simr = to_imx8ulp_sim_reset(rcdev);
+ const u32 bit = imx8ulp_sim_reset_bits[id];
+
+ return regmap_update_bits(simr->regmap, AVD_SIM_SYSCTRL0, bit, 0);
+}
+
+static int imx8ulp_sim_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct imx8ulp_sim_reset *simr = to_imx8ulp_sim_reset(rcdev);
+ const u32 bit = imx8ulp_sim_reset_bits[id];
+
+ return regmap_update_bits(simr->regmap, AVD_SIM_SYSCTRL0, bit, bit);
+}
+
+static const struct reset_control_ops imx8ulp_sim_reset_ops = {
+ .assert = imx8ulp_sim_reset_assert,
+ .deassert = imx8ulp_sim_reset_deassert,
+};
+
+static const struct of_device_id imx8ulp_sim_reset_dt_ids[] = {
+ { .compatible = "nxp,imx8ulp-avd-sim-reset", },
+ { /* sentinel */ },
+};
+
+static int imx8ulp_sim_reset_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct imx8ulp_sim_reset *simr;
+ int ret;
+
+ simr = devm_kzalloc(dev, sizeof(*simr), GFP_KERNEL);
+ if (!simr)
+ return -ENOMEM;
+
+ simr->regmap = syscon_node_to_regmap(dev->of_node);
+ if (IS_ERR(simr->regmap))
+ return dev_err_probe(&pdev->dev, PTR_ERR(simr->regmap),
+ "failed to get regmap\n");
+
+ simr->rcdev.owner = THIS_MODULE;
+ simr->rcdev.nr_resets = IMX8ULP_SIM_RESET_NUM;
+ simr->rcdev.ops = &imx8ulp_sim_reset_ops;
+ simr->rcdev.of_node = dev->of_node;
+
+ ret = devm_of_platform_populate(dev);
+ if (ret)
+ return ret;
+
+ return devm_reset_controller_register(dev, &simr->rcdev);
+}
+
+static struct platform_driver imx8ulp_sim_reset_driver = {
+ .probe = imx8ulp_sim_reset_probe,
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .of_match_table = imx8ulp_sim_reset_dt_ids,
+ },
+};
+module_platform_driver(imx8ulp_sim_reset_driver);
+
+MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>");
+MODULE_DESCRIPTION("NXP i.MX8ULP System Integration Module Reset driver");
+MODULE_LICENSE("GPL");