From patchwork Tue Sep 17 16:44:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jason-JH.Lin" X-Patchwork-Id: 13806351 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66272CAC590 for ; Tue, 17 Sep 2024 16:46:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-Transfer-Encoding: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=+1AC3fNP1VonWnj0josaocduyAD66sB5A6D1HOYbBnE=; b=RN615wMKV58GsGTPdRD4H3CFwa dfQPBA9blB0TSNzE6xr8ep7O8o5kuSQuWodadm4DzudJ/jINCEcLa+F0uXsssopsihuifPFLipLbk ovqXPDYlRv/6rnyYBLYm3PRYojUkA8yycdQrj7O72k1cEXrBILtlBN6IBJYNllJF6e8b8LMuRrzLC i0cxqkElwIpOMjSKNP0x/5lTRSXoFFJto7jLfGOT9AtD7JQTDqkIntvwS0twfPLNNQr/+XojFIlQh 8vjmLlBmisOGSMka6K58htFM09/NOqROG60CAE5qG8wH+OAKobmPpK5bspNKcJtWc2tHdsdpD9Ls2 Pba1WGoA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1sqbLh-00000006XWX-3nAl; Tue, 17 Sep 2024 16:46:45 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1sqbJl-00000006XBp-1aWa; Tue, 17 Sep 2024 16:44:47 +0000 X-UUID: 224417f8751411efba0aef63c0775dbf-20240917 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=+1AC3fNP1VonWnj0josaocduyAD66sB5A6D1HOYbBnE=; b=Op30LpBsEhZzODLq1qGLtwxw149WW+50FeZLzbCN31ZERK90feAXS6Z3RDPkzzbmH56L9mEWfJGT6r+YdaCelsXwRYzwx63qOA7vfEv+e1ffCcba2BrzsxCwNQhGieJlASF3twKeT1Voj0bp82aPDKqP2drUrrYb1lZjptqwsNg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.41,REQID:4f1c2486-f278-4e9d-9a6f-a8ddfbaae413,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:6dc6a47,CLOUDID:f22a55d0-7921-4900-88a1-3aef019a55ce,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 224417f8751411efba0aef63c0775dbf-20240917 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 908541089; Tue, 17 Sep 2024 09:44:40 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 18 Sep 2024 00:44:36 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 18 Sep 2024 00:44:36 +0800 From: Jason-JH.Lin To: Alper Nebi Yasak , Chun-Kuang Hu , AngeloGioacchino Del Regno CC: Shawn Sung , , , , , "Jason-JH . Lin" , Singo Chang , "Nancy Lin" , Subject: [PATCH v3] drm/mediatek: ovl: Add fmt_convert function pointer to driver data Date: Wed, 18 Sep 2024 00:44:34 +0800 Message-ID: <20240917164434.17794-1-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--12.162200-8.000000 X-TMASE-MatchedRID: 4LZxuBlJqUUzP1+hKLmUcMu00lnG8+PWIaLR+2xKRDLb6Y+fnTZULz94 HX24gqtCCInppypKAT/VoxB0j4x40LQ9EkyAW8JW2OSj4qJA9QbeHKxRMJ4P8diCsYPC4Ul22ft v/5jXki+muE8sHNH+0RUh680kRJ0sVWO7fs8MQC7k7k9yXJiqqhZO94uK1VSBWabPstVV86l6gt iEqf13+84WZ2e8JNtqZmkxQVgZGGRLdmeL82hot98tWTI1R8ep/5QRvrl2CZDzYcyIF7RSVb5Sd /nplJIc4vM1YF6AJbbCCfuIMF6xLSAHAopEd76vOhFpIr55H3NVjx/3+Flhi5F2YlOFSiZmwi3T t1ZQFjCcb1Pw5XWcDw== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--12.162200-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 4048DE2440AFB7BC677F4ECD18AB14426478FB263DF3AD24EB84EE36FFD723D02000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240917_094445_464529_53E627EB X-CRM114-Status: GOOD ( 17.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org OVL_CON_CLRFMT_MAN is a configuration for extending color format settings of DISP_REG_OVL_CON(n). It will change some of the original color format settings. Take the settings of (3 << 12) for example. - If OVL_CON_CLRFMT_MAN = 0 means OVL_CON_CLRFMT_RGBA8888. - If OVL_CON_CLRFMT_MAN = 1 means OVL_CON_CLRFMT_PARGB8888. Since OVL_CON_CLRFMT_MAN is not supported on previous SoCs, It breaks the OVL color format setting of MT8173. Therefore, the fmt_convert function pointer is added to the driver data and mtk_ovl_fmt_convert_with_blend is implemented for MT8192 and MT8195 that support OVL_CON_CLRFMT_MAN, and mtk_ovl_fmt_convert is implemented for other SoCs that do not support it to solve the degradation problem. Fixes: a3f7f7ef4bfe ("drm/mediatek: Support "Pre-multiplied" blending in OVL") Signed-off-by: Jason-JH.Lin Tested-by: Alper Nebi Yasak Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 63 ++++++++++++++++++++++--- 1 file changed, 56 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 89b439dcf3a6..4948f269fb81 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -143,6 +143,7 @@ struct mtk_disp_ovl_data { unsigned int addr; unsigned int gmc_bits; unsigned int layer_nr; + unsigned int (*fmt_convert)(struct device *dev, struct mtk_plane_state *state); bool fmt_rgb565_is_0; bool smi_id_en; bool supports_afbc; @@ -386,13 +387,54 @@ void mtk_ovl_layer_off(struct device *dev, unsigned int idx, DISP_REG_OVL_RDMA_CTRL(idx)); } -static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt, - unsigned int blend_mode) +static unsigned int mtk_ovl_fmt_convert(struct device *dev, struct mtk_plane_state *state) { - /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" - * is defined in mediatek HW data sheet. - * The alphabet order in XXX is no relation to data - * arrangement in memory. + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); + unsigned int fmt = state->pending.format; + + switch (fmt) { + default: + case DRM_FORMAT_RGB565: + return OVL_CON_CLRFMT_RGB565(ovl); + case DRM_FORMAT_BGR565: + return OVL_CON_CLRFMT_RGB565(ovl) | OVL_CON_BYTE_SWAP; + case DRM_FORMAT_RGB888: + return OVL_CON_CLRFMT_RGB888(ovl); + case DRM_FORMAT_BGR888: + return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP; + case DRM_FORMAT_RGBX8888: + case DRM_FORMAT_RGBA8888: + case DRM_FORMAT_RGBX1010102: + case DRM_FORMAT_RGBA1010102: + return OVL_CON_CLRFMT_RGBA8888; + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_ARGB2101010: + return OVL_CON_CLRFMT_ARGB8888; + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_ABGR2101010: + return OVL_CON_CLRFMT_ABGR8888; + case DRM_FORMAT_UYVY: + return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB; + case DRM_FORMAT_YUYV: + return OVL_CON_CLRFMT_YUYV | OVL_CON_MTX_YUV_TO_RGB; + } +} + +static unsigned int mtk_ovl_fmt_convert_with_blend(struct device *dev, + struct mtk_plane_state *state) +{ + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); + unsigned int fmt = state->pending.format; + unsigned int blend_mode = state->base.pixel_blend_mode; + + /* + * For the platforms where OVL_CON_CLRFMT_MAN is defined in the + * hardware data sheet and supports premultiplied color formats + * such as OVL_CON_CLRFMT_PRGB8888. */ switch (fmt) { default: @@ -471,7 +513,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx, return; } - con = ovl_fmt_convert(ovl, fmt, blend_mode); + con = ovl->data->fmt_convert(dev, state); if (state->base.fb) { con |= OVL_CON_AEN; con |= state->base.alpha & OVL_CON_ALPHA; @@ -625,6 +667,7 @@ static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = { .addr = DISP_REG_OVL_ADDR_MT2701, .gmc_bits = 8, .layer_nr = 4, + .fmt_convert = mtk_ovl_fmt_convert, .fmt_rgb565_is_0 = false, .formats = mt8173_formats, .num_formats = ARRAY_SIZE(mt8173_formats), @@ -634,6 +677,7 @@ static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = { .addr = DISP_REG_OVL_ADDR_MT8173, .gmc_bits = 8, .layer_nr = 4, + .fmt_convert = mtk_ovl_fmt_convert, .fmt_rgb565_is_0 = true, .formats = mt8173_formats, .num_formats = ARRAY_SIZE(mt8173_formats), @@ -643,6 +687,7 @@ static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { .addr = DISP_REG_OVL_ADDR_MT8173, .gmc_bits = 10, .layer_nr = 4, + .fmt_convert = mtk_ovl_fmt_convert, .fmt_rgb565_is_0 = true, .formats = mt8173_formats, .num_formats = ARRAY_SIZE(mt8173_formats), @@ -652,6 +697,7 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { .addr = DISP_REG_OVL_ADDR_MT8173, .gmc_bits = 10, .layer_nr = 2, + .fmt_convert = mtk_ovl_fmt_convert, .fmt_rgb565_is_0 = true, .formats = mt8173_formats, .num_formats = ARRAY_SIZE(mt8173_formats), @@ -661,6 +707,7 @@ static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = { .addr = DISP_REG_OVL_ADDR_MT8173, .gmc_bits = 10, .layer_nr = 4, + .fmt_convert = mtk_ovl_fmt_convert_with_blend, .fmt_rgb565_is_0 = true, .smi_id_en = true, .formats = mt8173_formats, @@ -671,6 +718,7 @@ static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = { .addr = DISP_REG_OVL_ADDR_MT8173, .gmc_bits = 10, .layer_nr = 2, + .fmt_convert = mtk_ovl_fmt_convert_with_blend, .fmt_rgb565_is_0 = true, .smi_id_en = true, .formats = mt8173_formats, @@ -681,6 +729,7 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = { .addr = DISP_REG_OVL_ADDR_MT8173, .gmc_bits = 10, .layer_nr = 4, + .fmt_convert = mtk_ovl_fmt_convert_with_blend, .fmt_rgb565_is_0 = true, .smi_id_en = true, .supports_afbc = true,