From patchwork Wed Sep 18 08:27:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Dahl X-Patchwork-Id: 13806693 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C8860CCD18E for ; Wed, 18 Sep 2024 08:30:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-Id:Date :Subject:To:From:Reply-To:Content-Type:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pDXpXaegpKO5X3zQrD+t/zmtDNYbjkoQfmdIzd6/8JQ=; b=MpcFJ+RH2p4Ha5 CjCK3Ojb9xEBKEq5gNTBGRjQ85x4aq6BBruk6/2LFIlvv947lA7i7ynv9H7vdhFLWYboFTVs2clf7 mMQx27sFNh/jY4HHciEySGMnsMu7TXwiLVDL3NF7JVYf2qQ6xhv1R7Nk6+jvWeTZx5fR6HHfsLtaJ d58L7QzSlYaxTOw6dJcT9GPXHZGwfNVpE/Qs817u51lS+DxgP3Hx58FwgHk463yvpJAuGkcbGbWeA IzUiAGroPtqL3l2RvtupM+JZFM9adXtJ8UMPXVf18XvJ/l68LlXPHBcdB6v+Fj58nxjQ5Z+MPLgfJ V+4msl7PypGbDndZxNZA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1sqq4f-00000007odU-0Lhr; Wed, 18 Sep 2024 08:30:09 +0000 Received: from mail.thorsis.com ([2003:a:e28:26e4::10]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1sqq2U-00000007oCx-1cFu for linux-arm-kernel@lists.infradead.org; Wed, 18 Sep 2024 08:27:55 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 176621489929; Wed, 18 Sep 2024 10:27:50 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=thorsis.com; s=dkim; t=1726648071; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=pDXpXaegpKO5X3zQrD+t/zmtDNYbjkoQfmdIzd6/8JQ=; b=BSM3cBMiUjsPpzVfdToqqaltViOeVW8dbHHUscPQ4wWHOXXpyIOUw2mPX3e2KSu8xx5I0z CtqlKNxjPhquZf6kynj//g9uqZw7/8vjmj8OlOKgz11sfdfD7UheSigFlZsDGiANm/2vtO 9pLukICPBHFxXrd7iHrrckOwE+dDuM+IX3LezcOQN3KBojOwoXD7z3t9RTZoOVEaYs8F2E RIej78z81eOZOxDfNCGS3zzCuAz0l+zCLYWT2TTKwWQ9G+NqwVd85y1kyMOCGUG4zJaKNj X0uGwtIIr2WsfjEWWQ+dcewnncPFOcwrKXFhRYYZuTUIzCXc0B8UCpXck/WUnA== From: Alexander Dahl To: Mark Brown Subject: [PATCH 1/2] spi: atmel-quadspi: Avoid overwriting delay register settings Date: Wed, 18 Sep 2024 10:27:43 +0200 Message-Id: <20240918082744.379610-2-ada@thorsis.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20240918082744.379610-1-ada@thorsis.com> References: <20240918082744.379610-1-ada@thorsis.com> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240918_012754_609559_BF7CBFF5 X-CRM114-Status: GOOD ( 13.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexandre Belloni , open list , "open list:SPI SUBSYSTEM" , Tudor Ambarus , Claudiu Beznea , "moderated list:ARM/Microchip AT91 SoC support" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Previously the MR and SCR registers were just set with the supposedly required values, from cached register values (cached reg content initialized to zero). All parts fixed here did not consider the current register (cache) content, which would make future support of cs_setup, cs_hold, and cs_inactive impossible. Setting SCBR in atmel_qspi_setup() erases a possible DLYBS setting from atmel_qspi_set_cs_timing(). The DLYBS setting is applied by ORing over the current setting, without resetting the bits first. All writes to MR did not consider possible settings of DLYCS and DLYBCT. Signed-off-by: Alexander Dahl Fixes: f732646d0ccd ("spi: atmel-quadspi: Add support for configuring CS timing") --- drivers/spi/atmel-quadspi.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index 5aaff3bee1b7..fcd57cf1f2cf 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -375,9 +375,9 @@ static int atmel_qspi_set_cfg(struct atmel_qspi *aq, * If the QSPI controller is set in regular SPI mode, set it in * Serial Memory Mode (SMM). */ - if (aq->mr != QSPI_MR_SMM) { - atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR); - aq->mr = QSPI_MR_SMM; + if (!(aq->mr & QSPI_MR_SMM)) { + aq->mr |= QSPI_MR_SMM; + atmel_qspi_write(aq->scr, aq, QSPI_MR); } /* Clear pending interrupts */ @@ -501,7 +501,8 @@ static int atmel_qspi_setup(struct spi_device *spi) if (ret < 0) return ret; - aq->scr = QSPI_SCR_SCBR(scbr); + aq->scr &= ~QSPI_SCR_SCBR_MASK; + aq->scr |= QSPI_SCR_SCBR(scbr); atmel_qspi_write(aq->scr, aq, QSPI_SCR); pm_runtime_mark_last_busy(ctrl->dev.parent); @@ -534,6 +535,7 @@ static int atmel_qspi_set_cs_timing(struct spi_device *spi) if (ret < 0) return ret; + aq->scr &= ~QSPI_SCR_DLYBS_MASK; aq->scr |= QSPI_SCR_DLYBS(cs_setup); atmel_qspi_write(aq->scr, aq, QSPI_SCR); @@ -549,8 +551,8 @@ static void atmel_qspi_init(struct atmel_qspi *aq) atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR); /* Set the QSPI controller by default in Serial Memory Mode */ - atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR); - aq->mr = QSPI_MR_SMM; + aq->mr |= QSPI_MR_SMM; + atmel_qspi_write(aq->mr, aq, QSPI_MR); /* Enable the QSPI controller */ atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);